MMIC yield optimisation by design centring and off-chip controllers G. Scotti, P. Tommasino and A. Trifiletti Abstract: The use of short-length III–V technologies is required to design circuits for microwave and millimetre-wave applications showing state-of-the-art performance. The parameter dispersion of such processes requires design techniques to achieve the best trade-off between performance and yield. External control of MMIC bias, based on process parameters estimation, allows yield enhancement even when design centring or feedback-based controls are not effective. A methodology to perform yield-oriented design of MMICs in III–V technologies is proposed. A set of on-chip circuits is used to estimate the value of process parameters; an external controller corrects the bias point in order to achieve the design centring in a parameter region around the estimated values. The proposed technique corrects circuit performance in the presence of parameter values belonging to the distribution tail, where standard techniques fail. The design centring approach and a distance-dependent correlated statistical model of HEMTs are used to design the external controller. The proposed methodology has been applied to design both a transimpedance amplifier and a distributed amplifier for multi-gigabit applications, showing a yield improvement of more than 10% with respect to the design centring approach, and encouraging the use of the proposed methodology for circuit design with short-length III–V technologies. 1 Introduction It is difficult to meet the performance requirements imposed by today’s microwave and millimetre–wave IC market. The best performance in terms of speed, noise or power handling capability is achieved by using innovative technologies such as short gate (i.e. lower than 0.2 mm) III–V based ones. These technologies are affected by process parameter dispersion [1] , which results in circuit performance variability and may prevent achievement of the desired yield. In order to obtain a good trade-off between performance and yield, a design flow in which statistical models of active devices are used jointly with yield optimisation techniques [2] is needed. Several approaches for statistical modelling of active devices in both linear and non-linear operation have been proposed [3–7] to perform circuit simulation. Different types of statistical models have been developed, based on a physical description of MESFET and HEMT devices, on measurement databases, or on empirical equivalent circuits. Recently, a nonlinear model in which correlation between parameters of devices on the same chip is assumed to be a function of the distances among the devices themselves, has been developed [8, 9] . The yield optimisation problem has been addressed and analytically formulated in [10], and various approaches, such as design centring [3] , [11] or DOE [12] , have been proposed to find CAD-oriented solutions. These techniques allow one to gain insight into the circuit behaviour but may not be suitable to enhance the yield of circuits that are very sensitive to DC parameter variations of the active devices. For instance, in DC-coupled topologies bias point variation of active devices strongly lowers the yield even if design centring is performed, and external control of the bias point is needed. Some techniques have been proposed to enhance yield by means of on-chip analogue bias regulators and/or feedback networks which allow reduction of the sensitivity of the circuit to DC parameter dispersion [2] . However, in complex circuits composed of DC-coupled amplifier stage, regulation of the DC current of a certain number of devices may be a suboptimal solution, which is not able to guarantee the maximal yield. A technique has been presented [2] to achieve bias stabilisation by means of feedback loops that estimate and correct the mean values of currents and/or voltages and does not require a knowledge of the statistical behaviour of device parameters. However, the effects on yield of the mismatch among devices on the chip are not accounted for. A more rigorous approach requires a statistical model able to describe on-chip variations of device parameters. Recently a novel yield optimisation strategy, based on control of the MMIC bias performed by means of on-chip process parameter estimators and an external digital controller, has been presented [13] . In this paper, a detailed design methodology is proposed which allows one to determine the bias controlling function to be implemented into the digital controller, by analytically formulating the optimisation problem to be solved. The advantages of the new approach are demonstrated from the viewpoint of design centring theory. 2 Automatic estimation and correction of process variations A certain number of levels can be considered in the production flow of integrated circuits. Different lots of wafers are fabricated in different foundry runs. During each The authors are with the Department of Electronic Engineering, University of Rome ‘La Sapienza’, Via Eudossiana 18, Roma I-00184, Italy r IEE, 2005 IEE Proceedings online no. 20040788 doi:10.1049/ip-cds:20040788 Paper received 27th October 2003 54 IEE Proc.-Circuits Devices Syst., Vol. 152, No. 1, February 2005