BIAS CORRECTION AND YIELD OPTIMIZATION OF MMICs WITH EXTERNAL DIGITAL CONTROL Giuseppe Scotti, 1 Pasquale Tommasino, 1 and Alessandro Triﬁletti 1 1 Dipartimento di Ingegneria Elettronica Universita di Roma ‘‘La Sapienza’’ ` 00184 Roma, Italy Recei  ed 11 May 2001 ABSTRACT: A new methodology for yield optimization of integrated circuits is presented. We propose a dc external control scheme which performs on-line estimation of the acti  e de ice model parameters and proper correction of the bias point. Design of a 2.5 Gbit  s front-end ampliﬁer has been performed, and a strong yield impro  ement has been found.  2001 John Wiley & Sons, Inc. Microwave Opt Technol Lett 31: 134137, 2001. Key words: MMIC; yield; statistical model 1. INTRODUCTION In recent years, the use of short-gate III  V technologies for microwave and millimeter-wave integrated circuits has been rapidly increasing due to their challenging performance in terms of f and noise ﬁgure. As a drawback, a wide disper- T sion of process parameters results in gate threshold variations as high as some hundred millivolts, together with strong variations of other parameters. Such process parameter dis- persion implies that designers have to ﬁnd a hard tradeoff between performance and yield, by means of accurate statisti- cal models of active devices andor bias regulators. In the last two decades, several physical and empirical   statistical models 1  7 have been proposed for FET devices. They usually account for the linear behavior of the device itself, and allow circuit simulation within commercial CAD tools. Recently, methodologies also have been proposed to   achieve nonlinear statistical empirical models 8  9 . In partic- ular, an instantaneous empirical model and a procedure to   extract its parameters have been developed 10  11 . For what concerns bias regulators, the necessity of their   integration was addressed in 12 , where the size of a typical hybrid current regulator was shown to be 25 times greater than an MMIC with a monolithic regulator. A feedback-based current regulator was proposed and applied to the design of a single-stage low-noise ampliﬁer. The technique was then ex-   tended in 13 to the design of a multistage ampliﬁer. This technique has proved to be very powerful, having regulated current errors lower than 3% over a 0.5 V threshold voltage variation. Unfortunately, in complex circuits com- posed of dc-coupled ampliﬁer stages, based on differential pairs andor feedback-based topologies such as the trans- Ž impedance ampliﬁer e.g., circuits for digital optical commu- . nication systems , the regulation of the dc current of a certain number of devices may be a suboptimal solution which is not able to guarantee the maximal yield. In this paper, we propose an alternative solution based on the external control of circuit bias, performed by means of on-chip process parameter estimators and a dc control chip. During MMIC operation, the controller estimates parameters and corrects the bias point in order to maximize the circuit yield. It has to be remarked that the availability of low-cost, small size, and low-spread silicon chips, able to perform the Ž required dc elaboration i.e., AD and DA conversion, control- . ling, etc. , makes this solution challenging. In Section 2, a review of the techniques used to estimate and model process parameter dispersion is reported. In Section 3, a yield-ori- ented methodology to design MMICs is presented, which makes use of an empirical nonlinear statistical model and a control scheme composed of both an on-chip model parame- ter estimator and a control chip. In Section 4, details are reported on the practical feasibility of variable estimators for the statistical model in Section 3. Finally, in Section 5, a case study concerning the design of a front-end ampliﬁer for digital optical communication systems is presented to high- light the advantages of the proposed approach. 2. ESTIMATION OF PROCESS PARAMETER DISPERSION A yield-oriented MMIC design requires the accurate estima- tion and modeling of process parameter dispersion, so that the inﬂuence on performance may be evaluated and limited. The global distribution of process parameters, together with both interwafer and intrachip distributions, is needed: it can be supposed that active devices on the same chip show lower dispersion than devices on different wafers or belonging to different runs. Therefore, a circuit analysis based on a global process distribution leads to a pessimistic evaluation of yield. A more accurate statistical model has to be able to divide the distribution of parameter p into a large-scale portion p LS which takes into account the global and interwafer disper- sions, and a small-scale portion p represents intrachip SS dispersion: Ž. p  p  p 1 LS SS where p is a zero mean-value distribution. SS Typically used design approaches do not require the esti- mation of statistical parameters p, and only need estimation and correction of their mean values by means of feedback   loops 12  13 , as described in Section 1. These methods allow the evaluation of the obtained distribution of corrected pa- rameters, but not the effect on overall yield. A more rigorous approach would evaluate the distribution of parameters p by developing a statistical model which accounts for both large- scale dispersion and correlation among devices on the same chip: unfortunately, a huge number of measurements per- formed on different wafers is required to achieve the statisti- cal population needed to extract the model. Moreover, the use of such a model permits accurate evaluation, but not optimization of circuit yield. A different approach is proposed in this work, based on the observation that a much larger variance is found for large-scale variable p with respect to LS intrachip variations p ; therefore, we propose a more effec- SS tive approach to yield optimization which requires the on-chip estimation and correction of large-scale dispersion, and accu- rate modeling of intrachip variations which cannot be cor- rected. The proposed approach, described in Section 3, makes use of an external control circuit to provide postfabrication correction of large-scale dispersion, and a small-scale statisti- cal model extracted from a single test chip to evaluate and optimize circuit yield. This methodology permits us to obtain yield values higher than those found with previously de- scribed techniques which make use of feedback loops. 3. PROPOSED DESIGN METHODOLOGY The yield-oriented design methodology presented in this pa- per requires us to both develop a statistical model able to MICROWAVE AND OPTICAL TECHNOLOGY LETTERS / Vol. 31, No. 2, October 20 2001 134