Journal of Biosciences and Medicines, 2013, 1, 1-5 JBM http://dx.doi.org/10.4236/jbm.2013.12001 Published Online October 2013 (http://www.scirp.org/journal/jbm/ ) OPEN ACCESS A spatiotemporal signal processing technique for wafer-scale IC thermomechanical stress monitoring by an infrared camera Michel Saydé, Ahmed Lakhssassi, Emmanuel Kengne, Roman Palenichka Department of Computer Sciences and engineering, University of Quebec at Outaouais, Gatineau, Canada Email: michel.sayde@uqo.ca , ahmed.lakhssassi@uqo.ca , kengem01@uqo.ca , Roman.Palenichka@uqo.ca Received July 2013 ABSTRACT In this paper, we describe a new silicon-die thermal monitoring approach using spatiotemporal signal processing technique for Wafer-Scale IC thermome- chanical stress monitoring. It is proposed in the con- text of a wafer-scale-based (WaferIC TM ) rapid proto- typing platform for electronic systems. This technique will be embedded into the structure of the WaferIC, and will be used as a preventive measure to protect the wafer from possible damages that can be caused by excessive thermomechanical stress. The paper also presents spatial and spatiotemporal algorithms and the experimental results from an IR images collection campaign conducted using an IR camera. Keywords: Thermal Monitoring; Ring Oscillator (RO); Spatial; Spatiotemporal; Thermo-Mechanical Stress; Temperature Sensor; Thermal Analysis; WaferIC; Wafer-Scale System 1. INTRODUCTION An innovative reconfigurable Wafer-Scale Integrated Circuit (WaferIC) for rapid electronic systems prototyp- ing has been introduced [1-3]. Electronic components can be placed anywhere at the smart active surface of the WaferIC. Then those components can be detected, pow- ered and interconnected through a complex but regular reconfigurable network laid over the surface of the WaferIC. As power consumption depends on user chips location and power pins distribution, it is not evenly dis- tributed throughout the surface of the silicon wafer. In many cases, it is unpredictable and variable as power consumption of programmable or dynamic components (e.g. microcontrollers) depends on their activities. There- fore, managing thermomechanical stress is a real chal- lenge and it may need to be monitored at all time in high performance applications. Thermal monitoring is essential in high performance integrated structures implemented as multilayer struc- tures composed of different materials. An increase of the internal temperature of some circuits can lead to signifi- cant thermal and thermo-mechanical problems. Under- standing thermal phenomena occurring on a micro-scale level is essential for SoC and MEMS-based applications. Thus, measurement techniques are needed to validate models predicting thermal behavior of integrated struc- tures. In particular, measurement techniques are needed to obtain surface temperature distributions of large inte- grated structures. Due to technology scaling, power density of high per- formance integrated structures has increased drastically. For example, the power density of high performance microprocessors has already reached 50 W/cm 2 at 100 nm technology and was forecasted to reach 100 W/cm 2 at 20 nm technology. Meanwhile, to mitigate the overall power consumption, many low power techniques have been proposed [4-10]. These techniques, though helpful to reduce the overall power consumption, may cause sig- nificant on-chip thermal gradients and local hot spots due to different clock/power gating activities and varying voltage scaling. It has been reported in [11] that temper- ature variations of 30˚C can occur in a high performance microprocessor design. The magnitude of thermal gra- dients and associated thermo-mechanical stress is ex- pected to increase further as VLSI designs move into nanometer processes and multi-GHz frequencies. The WaferIC is a LAIC (Large Area Integrated Cir- cuit). As a LAIC the increase of the power consumption and uIC disposition on the surface of the WaferIC will cause decrease in the wafer performance and the latency. In addition, 50% of the failure in the electronic device is due to the increase of the internal temperature of the chip [12]. However, the WaferIC must be able to support a large temperature differential at its surface [13]. There- fore, in this paper we propose a spatiotemporal signal processing technique for Wafer-Scale IC thermomechan- ical stress monitoring by an infrared camera. The tech-