26 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 58, NO. 1, JANUARY 2011 Nanowire to Single-Electron Transistor Transition in Trigate SOI MOSFETs Nima Dehdashti Akhavan, Aryan Afzalian, Member, IEEE, Chi-Woo Lee, Ran Yan, Isabelle Ferain, Pedram Razavi, Ran Yu, Giorgos Fagas, and Jean-Pierre Colinge, Fellow, IEEE Abstract—We investigate the effect of symmetrical geometrical constrictions on the electrical characteristics of ultrathin silicon- on-insulator nanowires with a trigate structure using a 3-D nu- merical quantum simulator. Introducing barriers at the source and drain junctions profoundly alter the device physics and a transition from 1-D to 0-D quantum behavior is observed. The con- strictions create resonance levels in the channel region of nanowire due to confinement in the three directions of space, which, in turn, causes oscillation of the I D –V GS characteristic. Based on the observed characteristics, we derive a set of parameters that draws the line between 1-D and 0-D quantum behavior of silicon nanowire transistors. Index Terms—low-dimensional structures, low temperature, quantum transport, silicon nanowire transistor, tunnel-barrier field-effect transistor (FET), 3-D device modeling. I. I NTRODUCTION C ONSTANT downscaling of semiconductor devices and steady improvements in processing techniques has en- abled the fabrication of devices with nanometer feature size. In the case of silicon-on-insulator (SOI) MOSFETs, the reduc- tion in channel length has been accompanied by a reduction of semiconductor body thickness and width. This reduction of semiconductor silicon film thickness gives rise to carrier confinement in the directions perpendicular to current flow and to the formation of energy subbands. As a result, the impact of confinement on the device characteristics of ultrathin SOI multigate nanowire field-effect transistor (FET) is now at- tracting considerable interest [1]–[5]. These phenomena could be used potentially in energy level measurement (transport spectroscopy), single-electron transistor (SET) logic based on Manuscript received February 9, 2010; revised September 22, 2010; accepted September 28, 2010. Date of publication October 28, 2010; date of current version December 27, 2010. This work was supported in part by the Science Foundation Ireland under Grant 05/IN/I888: Advanced Scalable Silicon-on- Insulator Devices for Beyond-End-of-Roadmap Semiconductors and Grant 06/IN.1/I857: Semiconductor and Molecular Nanowire Simulation for Tech- nology Design, by the Program for Research in Third-Level Institutions, and by the European Union Seventh Framework Program through the Networks of Excellence NANOSIL and EUROSOI+ under Contract 216171 and Contract 216373. The review of this paper was arranged by Editor M. Reed. N. D. Akhavan, C.-W. Lee, R. Yan, I. Ferain, P. Razavi, R. Yu, G. Fagas, and J.-P. Colinge are with the Tyndall National Institute, University College Cork, Lee Maltings, Cork, Ireland. A. Afzalian was with the Tyndall National Institute, University College Cork, Lee Maltings, Cork, Ireland. He is now with the Laboratoire de Microélec- tronique, Université Catholique de Louvain, 1348 Louvain-la-Neuve, Belgium (e-mail: nima.dehdashti@tyndall.ie). Color versions of one or more of the figures in this paper are available online at http://ieeexplore.ieee.org. Digital Object Identifier 10.1109/TED.2010.2084390 Fig. 1. Schematic of the trigate nanowire FET used in this paper. The shaded area corresponds to the silicon region. subband filling effects, and subthreshold swing enhancement [6]–[8]. Recent advances in processing techniques based on SOI technology have made creating tunnel barrier junctions in the channel region of nanowire MOSFETs possible, and SET ef- fects have been observed in some of these devices. One can use insulating tunnel barriers or electrically induced potential barri- ers to create confinement [1], [2], [6], [9]–[11]. Employing the aforementioned methods, different groups have fabricated SOI nanowires with constrictions and tunnel barriers and reported the observation of quantum effects. Zimmerman et al. [12] fabricated and measured a Si-based single-electron nanowire structure, where they report Coulomb blockade operation and describe its dependence on electrostatically formed barriers at two sides of the channel region. Saitoh et al. [2] fabri- cated and measured tunnel-barrier transistors having a channel thickness of 8 nm. Oscillations in the I D –V GS characteristics were observed at 77 K, but no criteria for quantum operation of the structure were reported. However, modeling of such tunnel junctions or quantum dot structures is mostly limited to 1-D models that neither take into account the variations of geometry in the channel region nor perform full treatment of the electrostatics problem [13]. Here, we consider a trigate silicon nanowire structure with typical dimensions envisioned for nanoelectronics applications. Our device simulations show that by adjusting the width of confinement and barrier constrictions near the source and drain of the nanowire channel (Fig. 1), a regime is approached where 3-D confinement in the channel is observed and enhanced os- cillations in the drain current I D versus gate voltage V GS occur. This effect illustrates the transition of the trigate transistor 0018-9383/$26.00 © 2010 IEEE