566 IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, VOL. 10, NO. 5, OCTOBER 2002 Gate-Diffusion Input (GDI): A Power-Efficient Method for Digital Combinatorial Circuits Arkadiy Morgenshtein, Alexander Fish, and Israel A. Wagner Abstract—Gate diffusion input (GDI)—a new technique of low-power digital combinatorial circuit design—is described. This technique allows reducing power consumption, propagation delay, and area of digital circuits while maintaining low complexity of logic design. Performance comparison with traditional CMOS and various pass-transistor logic design techniques is presented. The different methods are compared with respect to the layout area, number of devices, delay, and power dissipation. Issues like technology compatibility, top-down design, and precomputing synthesis are discussed, showing advantages and drawbacks of GDI compared to other methods. Several logic circuits have been implemented in various design styles. Their properties are discussed, simulation results are re- ported, and measurements of a test chip are presented. Index Terms—Analysis, CMOS, delay, digital, low-power design, performance, VLSI. I. INTRODUCTION W HIS rapid development of portable digital applications, the demand for increasing speed, compact implementa- tion, and low power dissipation triggers numerous research ef- forts [1]–[3]. The wish to improve the performance of logic cir- cuits, once based on traditional CMOS technology, resulted in the development of many logic design techniques during the last two decades [17]. One form of logic that is popular in low-power digital circuits is pass-transistor logic (PTL). Formal methods for deriving pass-transistor logic have been presented for nMOS. They are based on the model, where a set of control signals is applied to the gates of nMOS transistors. Another set of data signals are applied to the sources of the n-transistors [1]. Many PTL circuit implementations have been proposed in the literature [1], [2], [4]–[6], [14]. Some of the main advantages of PTL over standard CMOS design are 1) high speed, due to the small node capacitances; 2) low power dissipation, as a result of the reduced number of transistors; and 3) lower interconnection effects [7], [8], due to a small area. However, most of the PTL implementations have two basic problems. First, the threshold drop across the single-channel pass transistors results in reduced current drive and hence slower Manuscript received May 1, 2001; revised January 26, 2002. A. Morgenshtein is with the Biomedical Engineering Department, Tech- nion–Israel Institute of Technology, Haifa 32000, Israel (e-mail: arkadiy@ tx.technion.ac.il). A. Fish is with the Electrical Engineering Department, Ben-Gurion Univer- sity, Israel (e-mail: afish@ee.bgu.ac.il). I. A. Wagner is with IBM Haifa Labs, Haifa University, Mount Carmel, Israel (e-mail: wagner@il.ibm.com). Digital Object Identifier 10.1109/TVLSI.2002.801578 operation at reduced supply voltages; this is particularly im- portant for low-power design since it is desirable to operate at the lowest possible voltage level. Second, since the “high” input voltage level at the regenerative inverters is not , the PMOS device in the inverter is not fully turned off, and hence direct-path static power dissipation could be significant [4]. There are many sorts of PTL techniques that intend to solve the problems mentioned above [5]. 1) Transmission gate CMOS (TG) uses transmission gate logic to realize complex logic functions using a small number of complementary transistors. It solves the problem of low logic level swing by using pMOS as well as nMOS [1]. 2) Complementary pass-transistor logic (CPL) features complementary inputs/outputs using nMOS pass-tran- sistor logic with CMOS output inverters. CPL’s most important feature is the small stack height and the internal node low swing, which contribute to lowering the power consumption. The CPL suffers from static power consumption due to the low swing at the gates of the output inverters. To lower the power consumption of CPL circuits, LCPL and SRPL circuit styles are used. Those styles contain pMOS restoration transistors or cross-coupled inverters (respectively). 3) Double pass-transistor logic (DPL) uses complementary transistors to keep full swing operation and reduce the dc power consumption. This eliminates the need for restora- tion circuitry. One disadvantage of DPL is the large area used due to the presence of pMOS transistors. An additional problem of existing PTL is top-down logic de- sign complexity, which prevents the pass transistors from cap- turing a major role in real logic LSIs [6]. One of the main reasons for this is that no simple and universal cell library is available for PTL-based design. This paper proposes a new low-power design technique that allows solving most of the problems mentioned above—gate diffusion input (GDI) technique. The GDI approach allows im- plementation of a wide range of complex logic functions using only two transistors. This method is suitable for design of fast, low-power circuits, using a reduced number of transistors (as compared to CMOS and existing PTL techniques), while im- proving logic level swing and static power characteristics and allowing simple top-down design by using small cell library. Section II presents basic GDI functions and their circuit prin- ciple. In Section III, a detailed analysis of GDI cell is presented. Section IV shows a design methodology for GDI circuitry. Com- parisons of some basic logic functions and high-level combina- torial circuits designed in CMOS, PTL, and GDI are discussed 1063-8210/02$17.00 © 2002 IEEE