B uilt around biological-like informa- tion-processing structures, artificial neural networks (ANNs) have demon- strated their power and usefulness in areas where identification and adaptability are most crucial. After sufficient training with a given set of problem data (using an arbitrary learn- ing rule), ANNs can independently form inter- nal representations (models) of the data’s underlying phenomenon. Current neural net- work applications are in pattern recognition, function approximation, optimization prob- lems, and forecasting. For instance, due to their associative capability and after fine-tun- ing by sufficient training, ANNs can easily rec- ognize geometrical patterns and plain characters. The usefulness of ANNs arises from their adaptive and associative structure and their parallel and distributed model of computa- tion. Also, these networks have proven fault tolerant, as the failure of few elements (in large ANNs and in certain layers) does not significantly affect the network’s functional characteristics or performance. Furthermore, they can be easily designed to incorporate an even larger fault tolerance capability to achieve higher reliability. 1 ANNs typically have a large number of highly interconnected processing elements, which constrains their hardware implemen- tation and network architecture. To obtain high density and processing-element con- nectivity, most ANN architectures employ some kind of resource sharing. A multilayer structure allows processing elements to share communication lines and control cir- cuitry, so we chose to develop a multilay- ered neuroprocessor based on pipelined time-step interneural communication. Other pulse stream architectures, such as those proposed by Murray et al., 2 use the rate of impulses to represent the neural states. Our architecture, however, represents the neural states through pulse amplitude modulation. Also, in our design, the analog computation consists of integrating the bipo- lar input pulses corresponding to the exci- tatory and inhibitory activations. The processing-element analog path consists of CMOS transmission gates controlled by buffered signals originating from the neuro- processor control unit. The processing ele- ments broadcast their output states, held on a local capacitor, during their assigned time slots. These features are desirable to meet the design goals of versatility, high density, high connectivity, and scalability. Neuroprocessor architecture Figure 1 shows the topology of our mul- tilayered neural network. Using time-multi- plexed pulse stream communication, the processing elements of adjacent layers share communication lines along which they broadcast their output states during their assigned time slots. The time slot assignment is done by programming a cyclic shift regis- ter that holds the processing-element addresses in the programmed sequence. Our design uses bit-serial downloading of the network weights, which considerably reduces the addressing hardware require- ments. The analog processing-element out- puts are available for external monitoring or storage through the layer communication lines. Global clocks and signals are buffered and routed to each processing element. 58 IEEE M icro 0272-1732/97/$10.00 © 1997 IEEE For efficient chip area use and operating speed, this multi- layered pulse stream neuroprocessor design uses a mixed analog-digital implementation. A T IME -M ULTIPLEXED R ECONFIGURABLE N EUROPROCESSOR Fadi N. Sibai Intel Sunil D. Kulkarni Voice-Tel Enterprises .