Implementation of Control Algorithms in a System-on-a-Programmable-Chip Maciej Petko Grzegorz Karpiel Dept. of Robotics and Machine Dynamics Dept. of Robotics and Machine Dynamics AGH University of Science and Technology AGH University of Science and Technology al. Mickiewicza 30, 30-059 Krakow al. Mickiewicza 30, 30-059 Krakow Poland Poland petko@agh.edu.pl gkarpiel@agh.edu.pl Abstract – The paper presents problems related to implementation of control algorithms in FPGA. Proposed solution is based on System-on-Programmable-Chip architecture with soft-processor that allows for mixed, hardware/software implementation and exploration of possible control algorithm realizations. The case study is a neural controller for 3-DOF parallel robot for milling. The controller is based on neural model of the inverse dynamics of the manipulator, trained on data collected with the use of a computed torque stabilizing controller. For comparison, both controllers were implemented in a system of the same architecture. I INTRODUCTION Controller is an important part of mechatronic system, thus its implementation should be taken into account throughout the entire design process, especially when the target hardware platform is based on FPGA (Field Programmable Gate Array), which imposes non trivial constraints on control algorithm [1]. Control algorithm, to be implemented in FPGA is usually a continuous-time and continuous-value system, described by a set of mathematical equations or by a block diagram. Since such form is not appropriate for implementation, it requires several transformations, which influence not only the notation, but also the algorithm itself. First of all the time discretization is needed. The second substantial transformation is amplitude discretization (quantization). The use of only fixed-point arithmetic allows for significant reduction of algorithm realization cost. Nevertheless, care should be taken, because fixed- point representation can hardly cope with signals of high dynamics (which amplitude changes over several orders of magnitude). Its functioning is also influenced by phenomena peculiar to fixed-point calculations as overflow and saturation. For this reason performance of the algorithm after above transformation should be checked. EDA (Electronic Design Automation) tools used for synthesis of FPGA programming files accept chips descriptions in one of HDLs (Hardware Description Language). Coding in HDL is time consuming and error prone task. When using such notation, problem arises with testing and verification of algorithm performance. Existing attempts to create high-level language [2] allowing for simulation of FPGA on an algorithm level, are usually a mutation of C/C++ programming language, e.g. A|RT Library [3], SystemC [4], Handel-C [5], Cbridge [6], Bach. Recently, some tools have become available, which support synthesis from such description. However, these languages differ from standard C/C++ to the extent preventing simulation of the code outside specialized simulators. Tools, such as DSP Builder [7] and Xilinx System Generator [8] can synthesize FPGA programming files directly from Simulink model, but they are restricted regarding available algorithms (usually telecommunication oriented) and can target only specific FPGA families, as being created by chip manufacturers. In a case of complex control strategies, it is not always profitable to implement entire algorithm in hardware, especially those fragments that are of irregular structure or hard to transform to fixed-point form. The best solution then seems to be mixed, hardware/software realization. It has become possible as modern FPGAs allow for including inside entire system with microprocerssor(s), digital peripherals and custom signal processing blocks. II SYSTEM-ON-A-PROGRAMMABLE-CHIP IMPLEMENTATION System-on-Chip (SoC) is a single device (chip) that contains entire system: microprocessor(s), signal processing engines, peripherals, memory, standard communication interfaces, etc., custom tailored to a given task or class of tasks. Ability to implement SoC in FPGA (which is also called System-on-Programmable-Chip – SoPC) gives additional flexibility regarding experimenting with performance characteristic, even late in the design process, extending product life cycle by providing hardware and software upgrades, or adapting the feature set to specific demands of particular customer or application, without printed circuit board (PCB) modification. In the traditional SoC design method, designer has to manually write top level HDL files to connect together the pieces of the system and to implement data exchange, synchronization and arbitration. This approach requires a lot of effort and time. During last years tools facilitating system integration, as Xilinx’s ISE [8] or Altera’s SOPC Builder [7], became available. Using them, designer is freed from most tedious tasks and can concentrate on system architecture. Existing possibilities will be further explained on an example of SoPC based on Altera Stratix FPGA, Nios II 32-bit RISC soft-processor (i.e., not fixed in silicone) and SOPC Builder. Using SOPC Builder, designer specifies the system components in a graphical user interface (GUI), and SOPC Builder generates the interconnect logic automatically. SOPC Builder outputs HDL files that define all components of the system, and a top-level HDL design file that connects