Semi-Automatic Implementation of Control Algorithms in ASIC/FPGA Maciej Petko, Grzegorz Karpiel Dept. of Robotics and Machine Dynamics AGH University of Science and Technology al. Mickiewicza 30, 30-059 Krakow POLAND Abstract − In the paper, a procedure of semi-automatic hardware implementation of control algorithms is presented. Important role in this procedure plays generator of ASIC/FPGA synthesisable code from Simulink model. Virtual prototyping of entire mechatronic system is possible, including bit- and cycle-accurate simulation of hardware-implemented controller in Simulink. As a case study, nonlinear PID control of prismatic robot link with friction is described. I. INTRODUCTION Nowadays, controller should be considered as a part of mechatronic system and controller development as a mechatronic process. It means that during controller development a synergism should be achieved by integration of mechanical, electrical and electronic engineering together with automatics and information technology, and by treating them with equal importance [1]. The typical mechatronic system consists of mechanical part excited by actuators. The state of mechanical part is obtained by the means of sensors. The entire system is supervised by a control algorithm implemented and carried out on some hardware platform. In particular, this platform can be [2, 3] ASIC (application specific integrated circuit) or its programmable counterpart - FPGA (field programmable field array) based circuit. Such hardware is used for large lots production, and when high scale of integration and miniaturisation, or high reliability due to small number of components is required. The important problem restricting wider use of this platform is relatively high non-recurrent costs, related mainly to an implementation process, which is also time-consuming, error-prone and hard to integrate with the mechatronic design and development framework. An important stage of mechatronic design is virtual prototyping. It involves simulation of the entire system consisting of parts of various physical nature, and controller hardware and software. In mechatronics community, a popular platform for performing such a system-wide simulation is Simulink. It seems that out of diverse mechatronic system components, electronic, especially complex digital ones, are so far one of the hardest to simulate precisely and fast enough with the rest of a system. This integration weakness leads to increase of development costs and time to market. Another gap in the design process is lack of automatic implementation procedures in a case of control algorithm to be realized in increasingly popular FPGAs. The authors, aiming at simplification and automation of the process and its integration with standard mechatronic products development methods, have been developing a procedure of control algorithms implementation in ASIC/FPGA. This procedure can also be considered as fast prototyping on target hardware. After successful application for conventional [4, 5, 6], neural network [7] and fuzzy logic [8] based control, this procedure, recently augmented by automatic code generation, has been applied to a case study of prismatic robot link with friction. The rest of the paper is organized as follows. Section two introduces problems to be solved during controller implementation in FPGA, analyses available tools that can be used, and presents the objectives of developed implementation procedure, which is described in section three. In section four, the procedure is applied to a case study of a controller for a robot link with friction. The paper is summarized in section five. II. PROBLEM FORMULATION Control algorithm, to be implemented on FPGA/ASIC is usually a continuous-time and continuous-value system, described by a set of mathematical equations or by a block diagram. Since such form is not appropriate for implementation, it requires several transformations, which influence not only the notation, but also the algorithm itself. First of all the time discretization is needed. The second substantial transformation is amplitude discretization (quantization). The use of only fixed-point arithmetic allows for significant reduction of algorithm realization cost. Nevertheless, care should be taken, because fixed-point representation can hardly cope with signals of high dynamics (which amplitude changes over several orders of magnitude). Its functioning is also influenced by phenomena peculiar to fixed-point calculations as overflow and saturation. For this reason performance of the algorithm after above transformation should be checked. From this point of view, FPGA has the advantage over fixed-point microprocessor, as it allows for arbitrary, non-standard word length. Although transition between floating- and fixed- point realization cannot be fully automated, there are tools, e.g. Simulink Fixed Point Toolbox, CoCentric Fixed-Point Designer, A|RT Library [9, 10, 11], which help in carrying out this transformation. Additionally, problem appears with verification of fixed-point version of an algorithm compliance with its initial specification. EDA (Electronic Design Automation) tools used for synthesis of FPGA programming files or ASIC topology accepts chips descriptions in one of HDLs (Hardware Description Language). Coding in HDL is time consuming and error prone task. When using such notation, problem arises with testing and verification of algorithm performance. Existing attempts to create high-level language [12] allowing for simulation of FPGA/ASIC on an algorithm level, are usually a mutation of C/C++ programming language, e.g. A|RT Library, SystemC, Handel-C, Cbridge,