Understanding the Accellera SCE-MI Transaction Pipes John Stickley and Deepak Kumar Garg Mentor Graphics Brian Bailey Brian Bailey Consulting Jaekwang Lee and Amy Lim Cadence Design Systems Per Bojsen AMD Ramesh Chandra Qualcomm Ajeya Prabhakar Broadcom h THE RTL SIMULATOR has been the workhorse of functional verification for several decades, but as designs have become larger and the horsepower available in a single CPU has leveled off, the RTL simulator is no longer capable of keeping up with all of the demands placed on it. In order to mitigate this, many companies have been increasing their utilization of emulation, simulation acceleration and/or FPGA prototyping. We will collectively refer to these as hardware platforms and anything that runs on a general purpose computer as a software platform. The hardware platforms provide faster ex- ecution than the same design on a software platform although there are limitations related to the migra- tion of the design and testbench onto such plat- forms. Basically, the hardware platforms can only support what is currently synthesizable. While this subset has increased significantly over time, it is likely that at least part of the testbench cannot be synthesized and thus a mixed execution platform becomes necessary. When a mixed platform is deployed, there may be a significant execution speed disparity between the two sides. The hardware platform is able to exe- cute several orders of magnitude faster than an RTL simulator. Amdahl’s law states that the total speedup of a process is restricted by the piece that cannot be accelerated and so we need to find ways in which the best utilization of each piece of the mixed platform can be obtained. This is ideally obtained when there is an abstraction difference between the two sides of the platform di- vide. The portion that remains running on the software platform is modeled at a higher level of abstraction allowing it to execute significantly faster than an RTL simulation and is closer to the execution speed of the hardware platform running the RTL portion of the design. Having roughly matched the speed of execution on both pieces of the platform, we now turn our attention to the interface. In general, the model that bridges these abstraction differences is called a transactor. The transactor takes in high-level transac- tions on one of its interfaces and converts this to the necessary set of signal transitions on its second interface. Similarly signal transitions on the second interfaces are converted into transactions on the first interface. These transactors are an important part of most testbenches and have been integrated into Editors’ notes: Mixed platform for IP verification has become an increasingly important topic and the SCE-MI standard aims to solve communication issue between software and hardware parts of the platform. This paper is directed primarily towards infrastructure developers to better understand the SCE-MI stan- dard. Different configurations of the transaction pipes are described. VShishpal S. Rawat, Intel, and Sumit DasGupta, Si2 IEEE Design & Test of Computers 0740-7475/12/$31.00 B 2012 IEEE Copublished by the IEEE CEDA, IEEE CASS, and IEEE SSCS 32 EDA Industry Standards Digital Object Identifier 10.1109/MDT.2012.2184073 Date of publication: 12 January 2012; date of current version: 26 June 2012.