IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 51, NO. 11, NOVEMBER 2003 1761 A New Reconstruction Approach in the SRTS Method Jacqueline Walker, Member, IEEE, and Antonio Cantoni, Fellow, IEEE Abstract—The synchronous residual time stamp is widely imple- mented for the transport of the service clock associated with con- tinuous bit-rate services in asynchronous transfer mode adaptation layer 1. We present a new approach to service clock regeneration, which is simple to implement and can be proven to be correct. Index Terms—Asynchronous transfer mode (ATM), clock recovery, jitter, synchronization. I. INTRODUCTION A SYNCHRONOUS transfer mode (ATM) networks con- tinue to be deployed in access and backbone networks and are required to internetwork with existing communication net- works including the public switched telephone network (PSTN). The ATM application adaptation layer 1 (AAL1) has been de- fined [1] for the transport of continuous bit rate (CBR) signals in ATM, including a wide range of existing plesiochronous dig- ital hierarchy signals [2], [3]. Transport of CBR signals requires transfer of the timing infor- mation of the signal (the service clock) to allow reconstruction of the signal at the destination, and this function is an important aspect of the AAL1. Within the standard describing the AAL1, two methods have been approved for carrying out this task. The adaptive clock method is, in fact, a class of methods [1] in which the service clock is reconstructed at the receiver by adjusting a local clock so that the level of the receive buffer is maintained at a fixed level [1], [4], [5]. The second method proposed is the synchronous residual time stamp (SRTS) method [1], [6]–[8] which has been widely implemented. An important aspect of the SRTS method is the regeneration of the service clock at the destination. The earliest published regeneration technique appears in [6]. Other techniques for ser- vice regeneration have also appeared in patents [9]–[11]. In this letter, we present a new, simple-to-implement method of service clock regeneration, and we prove its correctness. The letter is organized as follows. In Section II, we provide a brief review of the SRTS method. In Section III, we present the new method of destination service clock recovery. Our conclusions are presented in Section IV. II. OVERVIEW OF THE SRTS METHOD End-to-end timing transfer for CBR services carried over AAL1 [1], [6] is achieved by sending information about the Paper approved by A. Pattavina, the Editor for Switching Architecture Per- formance of the IEEE Communications Society. Manuscript received February 2, 2002; revised October 30, 2002 and May 5, 2003. The work of J. Walker was supported in part by a grant from the Australian Telecommunications and Elec- tronics Research Board. J. Walker is with the Department of Electronic and Computer Engineering, University of Limerick, Limerick, Ireland (e-mail: jacqueline.walker@ul.ie). A. Cantoni is with the Western Australian Telecommunications Research In- stitute, Crawley 6009, Australia (e-mail: cantoni@watri.org.au). Digital Object Identifier 10.1109/TCOMM.2003.819209 Fig. 1. RTS generation in the SRTS method. associated clock, known as the service clock. Fig. 1 shows the essential elements involved in the SRTS method. A counter is clocked by a reference clock, which has a frequency of .A -bit latch is used to capture the value of the counter at regular instants of the service clock divided by . The output of the -bit latch is referred to as the residual time stamp (RTS). The block diagram in Fig. 1 also shows the need for a “syn- chronizer” to reduce the probability of metastable failure in RTS generation, as shown in [12]. Metastability occurs in latches when the input signals fail to meet setup and/or hold times with respect to the clock input, due to the asycnhronism between the input signals and the clock [13], [14]. Metastability cannot be eliminated when asynchronism exists, but can be managed so that the failure rate due to metastability can be controlled to an acceptable level by the use of an appropriate synchronizer. A timing diagram for the SRTS generation process is also shown in Fig. 1. The exact number of reference clock cycles in , one period of the divided-down service clock, is given by , which is normally not an integer. The integer part of , denoted by , is the number of reference clock cycles between successive latched -bit counter outputs. The value, which is the output of the -bit latch during the th interval, is related to as follows: modulo (1) where is the minimum number of bits to represent the RTS, where it is still uniquely identifiable [1], [6]. 0090-6778/03$17.00 © 2003 IEEE