ELSEVIER Microelectronic Engineering 46 (1999) 263-266 CMOS compatible alignment marks for the SCALPEL proof of lithography tool* MICROn.I~I'ilOII'IC R. C. Farrow, W. K. Waskiewicz, I. Kizilyalli, L. Ocola, J. Felker, C. Biddick, G. Gallatin, M. Mkrtchyan, M. Blakey, J. Kraus, A. Novembre, P. Orphanos, M. Peabody, R. Kasica, A. Kornblit, and F. Klemens Lucent Technologies, Bell Laboratories, Murray Hill, NJ 07974, USA SCALPEL alignment marks have been fabricated in a SiO2/WSi2 structure using SCALPEL lithography and plasma processing. The positions of the marks were detected through e-beam resist in the SCALPEL proof of lithography (SPOL) tool by scanning the image of the corresponding mask mark over the wafer mark and detecting the backscattered electron signal. Single scans of line space patterns yielded mark positions that were repeatable within 30 nm 30 with a dose of 0.4 gC/cm 2 and signal-to-noise of 16 dB. An analysis shows that the measured repeatability is consistent with a random noise limited response. The mark detection repeatability limit, that can be attributed to SPOL machine factors, was measured to be 20 nm 30. By using a digitally sequenced mark pattern, the capture range of the mark detection was increased to 13 ~tm while maintaining 36 nm 30 precision. The SPOL machine mark detection results are very promising considering that they were measured under electron optical conditions that were not optimized. 1. INTRODUCTION The SCALPEL lithography tool 1 uses alignment marks for many applications ranging from periodic setup and calibration to routine alignment and registration for achieving level to level overlay. A mark detection system was developed that uses the backscattered electron (BSE) signal generated from scanning the aerial image of a mask mark over a corresponding wafer mark? We performed an analysis of the mark material requirements assuming a SCALPEL tool operating under high throughput conditions. The result is that, to achieve a detectable signal with a signal-to-noise of at least 10 dB, the ratio of the mark BSE coefficient to the substrate must be a minimum of 0.01. Therefore, a large range of materials and geometries are acceptable as marks for SCALPEL. One of the important purposes of the SPOL tool 3 development is to provide experimental verification of the utility of the SCALPEL mark detection system for aligning integrated circuit (IC) critical levels at and below 0.1 ~m. In this paper we are reporting results from the first set of mark detection experiments where the SPOL tool was used to print and measure marks that were fabricated in material structures that are useful in CMOS IC's. These experiments were performed as a prelude to using SCALPEL to print the critical levels of an IC in a mix and match process. 2. MARK FABRICATION The marks were fabricated in a metal-oxide- semiconductor structure that is used in a variety of CMOS ICs. 4 The material stack was: Si-bulk/SiO:( 1000~,)/WSi: (2000A)/ARC (2200.A) The material was taken from actual wafer lots that would be suitable for exposure in a deep-ultraviolet (DUV) stepper. The antireflective coating (ARC) layer is not required for SCALPEL lithography. The wafers were coated with 0.5 gm of Sumitomo NEB-22A, a negative e-beam resist, and exposed in the SPOL tool using 4 mark patterns with each in a 9 X 9 array. After resist development the patterns were transferred to the WSie layer using plasma etching. After processing the wafers were coated with 0.36 gm of ARCH, a positive e-beam resist, and loaded in the SPOL tool for mark detection measurements. The final resist deposition was to simulate measurements under realistic *This work was supported, in part, by DARPA under Contract Number MDA972-98-C-007. 0167-9317/99/$ - see front matter © 1999 Elsevier Science B.V. All rights reserved. PII: S0167-9317(99)00077-5