A 0.5 V Fully Differential Gate-input Operational Transconductance Amplifier with Intrinsic Common-Mode Rejection Mustapha Abdulai and Peter Kinget Department of Electrical Engineering Columbia University New York, NY 10027, USA Abstract- In this paper we present an ultra-low voltage Here we report a more compact solution for a gate-input operational transconductance amplifier using gate-input OTA with intrinsic common-mode rejec- pMOS input devices and nMOS load devices with local tion. We use a pMOS input stage with nMOS loads common-mode feedback. This topology has a good intrinsic and local CMFB to provide good CM rejection. common-mode rejection. Simulations for a two-stage, 0.5 V fully differential operational transconductance amplifier A negative output conductance is further used to (OTA) with a gain of 55 dB and a common-mode rejection improve the differential-mode (DM) gain. ratio of 61 dB are reported. The amplifier consumes 77 pW OTAs are typically used in feedback applications, and has a gain-bandwidth product of 8.7 MHz when as shown in Fig. 1, with resistive, capacitive or designed in 0.18 pm CMOS technology. a combination of resistive and capacitive feedback and loading components. For a 0.5 V supply the I. INTRODUCTION common-mode level for the signals Vj, and V0,t to The current trend in CMOS feature size scaling obtain maximal swing is 0.25 V. Such common- into the nano-scale range and the required propor- mode level is however not sufficiently low to turn tional scaling in the power supply creates a demand on the standard pMOS input devices of the OTA. In for analog circuits that can operate at ultra-low a 0.18 ,um CMOS technology these devices have a supply voltages down to 0.5 V [1]. nominal IVTI of 0.5 V. The OTA presented here, like Fully differential OTA input stages typically use other gate-input OTAs [4], requires a level shifting a differential pair input stage biased with tail current between the common-mode level of the input signal source in combination with a common-mode feed- Vvg of the OTA and the common-mode levels of the back (CMFB) loop to provide a gain smaller than Vi, and V0,t signals as shown in Fig. 1 [6], [7]. For unity for common-mode (CM) signals in addition a 0.5 V supply, a 0.25 V common-mode level at the to a high common-mode rejection ratio (CMRR) Vi, and V0t, a 0.1 V common-mode level is obtained [2], [3]. For ultra-low supply operation down to at vg when using a resistor RB=2/33(Rl//R2) to 0.5 V, the tail current source needs to be removed sink a current to ground. Note that, as long as the to provide voltage headroom. However, the intrinsic loop gain is sufficiently large, the signal swing at the common-mode rejection present in a tail-biased OTA input is small so that a lower common-mode differential pair is then lost. In [4], the body of level can be used without restricting the maximal the input devices is used for the signal input in input or output signal swing. combination with a local output CMFB to the gates to achieve good CMRR and a common-mode gain I OPERATION OF THE BASIC STAGE smaller than 1. In [5], the input signal is applied to The first stage of the OTA, shown in Fig. 2, uses the gates of the input devices and common-mode pMOS input transistors M1 and M2 and operates rejection is achieved with a combination of local with a DC input common-mode of 0.1 V as de- CMFB and feed-forward cancellation. scribed above. Its output common-mode is set to 0-7803-9390-2/06/$20.00 ©)2006 IEEE 2837 ISCAS 2006