Copyright © 2018 A. S. S. Trinadh Kumar, B. V. V. Satyanarayana. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. International Journal of Engineering & Technology, 7 (3.29) (2018) 70-74 International Journal of Engineering & Technology Website: www.sciencepubco.com/index.php/IJET Research paper Low voltage high speed 8T SRAM cell for ultra-low power applications A. S. S. Trinadh Kumar 1 *, B. V. V. Satyanarayana 2 1,2 Department of ECE, Vishnu Institute of Technology, Bhimavaram, Andhra Pradesh, India *Corresponding author E-mail: somasekhar1024@gmail.com Abstract The usage of portable devices increasing rapidly in the modern life has led us to focus our attention to increase the performance of the SRAM circuits, especially for low power applications. Basically in six-Transistor (6T) SRAM cell either read or write operation can be performed at a time whereas, in 7T SRAM cell using single ended write operation and single ended read operation both write and read operations will be accomplished simultaneously at a time respectively. When it comes to operate in sub threshold region, single ended read operation will be degraded severely and single ended write operation will be severely degraded in terms of write-ability at lower voltages. To encounter these complications, an eight transistor SRAM cell is proposed. It performs single ended read operation and single ended write operation together even at sub threshold region down to 0.1V with improved read-ability using read assist and improved dynamic write-ability which helps in reducing the consumption of power by attaining a lower data retention voltage point. To reduce the total power consumption in the circuits, two extra access transistors are used in 8T SRAM cell which also helps in reducing the overall delay. Keywords: SRAM; Read-Ability; Write-Ability; Low Power; Read Assist; Pass Transistors and Delay. 1. Introduction Portable mobile electronic devices are mostly used in day to day lives which are equipped with batteries [1]. Power consumption is one of the main design metric in such devices. As power consump- tion increases, size of the battery and cost also increases, which in turn effects the compactness of the device. So, low power is the major requirement for portable systems. On the other side, Memory is the very important element in the embedded electronic systems which consume major part of system operation in terms of power. If the power consumption of memory is reduced, total power con- sumption [2] of system also reduced and hence size, cost, life and maintenance of the battery will be reduced and also system becomes more compact. Most of the researchers concentrated on low power memories for ultra-low power applications. In CMOS technology, SRAM circuit plays a vital role in digital sys- tems. The semiconductor type memory, which has bi stable latching circuitry is said to be Static Random Access Memory (SRAM). It can retain the data for one bit. SRAM cells are used for micro con- trollers and microprocessors. It mainly consists of two CMOS in- verters with back to back connection, these inverters act as a memory cell whereas the remaining transistors act as access tran- sistors. Bit and bit bar lines act as inputs and outputs. Every SRAM cell performs three basic operations, such as read, standby and write operations. In order to hold the data and to preserve the circuit in idle position, standby operation is performed. With the help of read- ability and write-ability, both read and write operations are per- formed in SRAM to read and write the data. In this paper, the power and delay are reduced in 8T SRAM cells when compared to stand- ard 6T SRAM cell and conventional 8T SRAM. Delay is reduced by using read assist technique and Power is condensed by using two extra pass transistors. Here, the length and width of PMOS with 0.13μm and 0.52μm are used and the length and width of NMOS with 0.13μm and 0.26μm are used respectively. 2. Literature review Gupta et al, [3] was proposed a scheme to increase the performance of seven transistor SRAM cell by performing read operation effi- ciently. But there is a delay during the read operation and the power dissipation is also very high. Budhaditya et al,[4] implemented a single bit line 6T SRAM cell, where there is high delay due to which the performance of read and write operations are severely degraded. Yang et al,[5] implemented 7T SRAM cell in Fin FET technology, but the power consumption is high. For low power applications An- sari et al, [6] designed a 7T SRAM cell, but didn’t calculate power and overall delay. For low power applications, an 8T SRAM cell is implemented in this paper by using Read assist 8T and two extra access transistors of 8T SRAM. We calculated and compared SRAM’s total power dissipation, read time, overall delay, write time and achieved low power consumption and lower delay com- paring to the earlier works. 3. Low power design requirements For portable devices, power is an important design consideration which plays a major role while designing VLSI circuits. There are different considerations that one would like to optimize about power. They are area, speed, testability, power dissipation, cost, risk and shielding. The power consideration is taken as an aspect along with the other two parameters: speed and chip design. a) Area Coming to the design considerations, area is directly proportional to the power. If the power consumption is reduced then the size of