Characterization of ultralow voltage, fully depleted silicon on insulator CMOS device and circuit technology q Huiling Shang a, * , Marvin H. White a , Dennis A. Adams b a Sherman Fairchild Lab, Lehigh University, Bethlehem, PA 18015, USA b Northrop Grumman Advanced Technology Center, Baltimore, MD 21203, USA Received 29 April 2002; accepted 7 May 2002 Abstract Wepresentthedesign,fabricationandcharacterizationoffullydepletedsilicononinsulator(FDSOI)CMOSdevices and circuits for ultralow voltage operation. We have obtained symmetrical threshold voltages for N and P channel devices with an ON–OFF current ratio of 1000:1. A figure of merit of 5 fJ/stage is achieved at 0.25 V on 0.25 lm,2- inputNANDgateFDSOICMOSringoscillators.Polysilicongatedepletionandsource–drainseriesresistancelimitthe performanceoftheFDSOICMOStechnology.Asimplifiedmodelcombinedwithhighfrequencycapacitance–voltage measurementsattwodifferentfrequenciesisdevelopedtodeterminetheseriesresistanceandpolysilicongatedepletion effects. Ó 2002 Elsevier Science Ltd. All rights reserved. 1. Introduction The trend to low voltage and low power has become increasingly important as microelectronics technology enters sub-100 nm arena, not only for mobile system to lengthenbatterylifebutalsoforhighperformancesystem reliability. Fully depleted silicon on insulator (FDSOI) devices have excellent characteristics for low power ap- plications,suchaslowsubthresholdslope,smallparasitic capacitance, high device packing density and complete isolation compared to bulk devices or partially depleted SOI devices [1]. FDSOI CMOS devices are ideal candi- datesforlowpower,high-speed,systemapplications.For ultralowvoltageoperation, V DD ’saslowas4kT =q (0.1V) have been reported for bulk CMOS technology using n-wellregulatorstomatchtheNMOSandPMOSOFF currents [2]; however, the area is doubled. With sym- metrical threshold voltage design of FDSOI CMOS de- vice [3,4], ultralow voltage, high-speed operation can be realizedwithFDSOICMOStechnology.Inthiswork,we describe the fabrication and characterization of FDSOI CMOSdevicestogetherwithcircuitoperationatsupply voltageaslowas0.25V.ForFDSOItechnology,asili- cideprocessisverycrucialtoachievelowparasiticseries resistance without consuming a large amount of the Si film[5,6].Inourdeviceswithplatinumsalicide,theseries resistanceisobservedwiththepolysilicongatedepletion effect from high frequency capacitance–voltage (HFCV) measurementsonMOScapacitors.Weshowbymodeling the maximum accumulation capacitance on MOS ca- pacitors that we can extract the series resistance and polysilicongatedepletioneffects. 2. Device fabrication Thestartingmaterialsare3in.SIMOXwaferswith t SI around100nmand t BOX around400nm.Thesiliconfilm is thinned down to 50 nm at 1000 °C by thermal oxi- dation.E-beamalignmentmarksarefirstdefinedonthe q This work has been supported by the Northrop Grumman Corporation through a grant from DARPA and Fellowships from the Sherman Fairchild Foundation and the Lucent Technologies. * Corresponding author. Present address: IBM T.J. Watson Research Center, Yorktown Heights, NY 10598, USA. Tel.: +1-914-945-1687; fax: +1-914-945-2141. E-mail address: shuiling@us.ibm.com (H. Shang). 0038-1101/02/$ - see front matter Ó 2002 Elsevier Science Ltd. All rights reserved. PII:S0038-1101(02)00235-6 Solid-State Electronics 46 (2002) 2307–2313 www.elsevier.com/locate/sse