An Efficient Methodology for Hierarchical Synthesis of Mixed-Signal Systems with Fully Integrated Building Block Topology Selection Tom Eeckelaert, Raf Schoofs, Georges Gielen, Michiel Steyaert, Willy Sansen Katholieke Universiteit Leuven, Department of Electrical Engineering, ESAT-MICAS Kasteelpark Arenberg 10, B-3001 Leuven Tom.Eeckelaert@esat.kuleuven.ac.be Abstract An hierarchical synthesis methodology for analog and mixed-signal systems is presented that fully in a novel way in- tegrates topology selection at all levels. A hierarchical system optimizer takes multiple topologies for all the building blocks at each hierarchical abstraction level, and generates opti- mal topology combinations using multi-objective evolution- ary optimization techniques. With the presented methodology, system-level performance trade-offs can be generated where each design point contains valuable information on how the systems performances are influenced by different combina- tions of lower-level building block topologies. The generated system designs can contain all kinds of topology combinations as long as critical inter-block constraints are met. Different topologies can be assigned to building blocks with the same functional behavior, leading to more optimal hybrid designs than typically obtained in manual designs. In the experimen- tal results, three different integrator topologies are used to generate an optimal system-level exploration trade-off for a complex high-speed ∆Σ A/D modulator. 1. Introduction The paper describes a novel analog synthesis methodology for mixed-signal systems that fully integrates topology selec- tion at all abstraction levels. It grants the analog designer access to the relation between the system-level performance behavior and the different building block topologies that can be used, for complex mixed-signal systems. To categorize the existing analog synthesis tools, first two tasks in the synthesis process have to be distinguished; the selection of a topology and the sizing of that selected topol- ogy. For those two tasks we can also distinguish between tools that are designed for circuit-level synthesis and tools that are designed for system-level synthesis. For example, tools like IDAC, OPASYN, OASYS, ANACONDA, AMGIE,. . . (see [8]) are circuit sizing tools where the topology is selected au- tomatically or interactively, and is sized according to given performance specifications. With tools like SEAS and DAR- WIN (see [8]) and the work of Koza [6], topologies can be generated or adapted during the sizing optimization process. However, these tools are targeted for circuits with a limited amount of design variables at the cell level e.g. integrators, comparators. For the design of mixed-signal systems at higher abstrac- tion levels e.g. data converters, the same distinction can be made between tools that select from a set of topologies (e.g. DAISY [4]), and recent methodologies that generate new system architectures using optimization techniques [7, 10]. These synthesis tools use a HDL language to describe the sys- tem and to generate new higher-level architectures. The hierarchical system exploration methodology de- scribed in this paper introduces an efficient way to explore different analog system architectures down to the transis- tor level where topology selection at all hierarchical abstrac- tion levels is fully integrated. With the methodology a set of optimal system-level performance samples are generated, where all the design points in this set contain information on the transistor-level topology combinations that are used to achieve the corresponding performance specifications. It is important to stress that the methodology explores the entire search space of design variables and circuit topologies at all levels. The methodology has the following novel features: • The designer’s insight in the relation between the system performance behavior and the selection of building block topologies at all levels is greatly improved. • Using evolutionary optimization techniques, hybrid com- binations of functionally the same building blocks can be generated, leading to more optimal designs than typically obtained in manual designs where often the same block is reused for reasons of convenience and time pressure. • Critical connection constraints from higher abstraction lev- els are efficiently taken into account during the lower-level topology selection process. This makes the methodology practically applicable as opposed to methodologies where sub-blocks are optimized separately and future inter-block constraints are difficult to satisfy. 1 978-3-9810801-2-4/DATE07 © 2007 EDAA