From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers Jie Han and Pieter Jonker Quantitative Imaging Group, Faculty of Applied Sciences, Delft University of Technology Lorentzweg 1, 2628 CJ, Delft, The Netherlands Emails: jie@ph.tn.tudelft.nl, pieter@ph.tn.tudelft.nl Abstract— Parallel processors such as SIMD computers have been successfully used in various areas of high performance image and data processing. Due to their characteristics of highly regular structures and mainly local interconnections, SIMD or SIMD-like architectures have been proposed for a large-scale integration of recently developed quantum and nanoelectronic devices. In this paper, we present a fault-tolerant technique suitable for an implementation in nanoelectronics, the triplicated interwoven redundancy (TIR). The TIR is a general class of triple modular redundancy (TMR), but implemented with random interconnections. A prototype structure for an image processor is proposed for the implementation of the TIR technique and a simulation based reliability model is used to investigate its fault- tolerance. The TIR is extended to higher orders, namely, the N-tuple interwoven redundancy (NIR), to achieve higher system reliabilities. It is shown that the reliability of a general TIR circuit is, in most cases, comparable with that of an equivalent TMR circuit, and that the design and implementation of restorative devices (voters) are important for the NIR (TIR) structure. Our study indicates that the NIR (TIR) is in particular suitable for an implementation by the manufacturing process of stochastically molecular assembly, and that it may be an effective fault- tolerant technique for a massively parallel architecture based on molecular or nanoelectronic devices. I. I NTRODUCTION Historically, parallel processing offered considerable per- formance advantages in many areas of computing. Several approaches have been explored and prototype systems were constructed. Among those, SIMD (single instruction and mul- tiple data) computers have been successfully used in various areas of data processing [1], [2]. The field of high performance image processing in particular has brought forward archetyp- ical systems (see, for examples, [3]-[6]). This evolvement of massively parallel processors have been based on the con- tinuous miniaturization of electronic components. As today’s CMOS technology enters the nanoelectronic realm (tens of nanometers and below), where quantum mechanical effects start to prevail, conventional CMOS devices are meeting many technological challenges for further scaling [7]. Novel infor- mation processing devices based on new physical phenomena have been investigated, and various novel architectures have been proposed for large-scale integration of these devices [8]. Recent progress in molecular electronics has in particular motivated much effort in the research of architectures that are suitable for the implementation of a nanoelectronic computer [9]-[11]. Due to the characteristics of many nanoelectronic devices, such as low power consumption, low drive capability and easy local interactions, parallel architectures that are highly regular and locally connected, have been studied as candidate architectures for nanocomputers. The architectural issues of a SIMD array have been discussed in [12] for nanoscale devices. Since molecular circuits are likely to be assembled through a bottom-up manufacturing process, in which randomness is inherent, imprecisions and inaccuracies seem to be inevitable in future nanoelectronic systems. Fault tolerance is thus a major issue in nanoarchitecture design [13]. Conventional fault-tolerant techniques, such as NAND multiplexing [14], N-tuple modular redundancy (e.g. triple modular redundancy (TMR)) [15] and reconfiguration, have been investigated for implementations in nanoelectronic systems [16]-[22]. A hi- erarchically reconfigurable architecture with the multiplexing technique implemented into the fundamental circuits has been studied for a system robust against both manufacturing defects and transient faults [23]. Von Neumann’s multiplexing technique is based on a mas- sive duplication of imperfect devices and randomized imper- fect interconnects. It has been shown that this construction can be reliable with a high probability, provided that the failure probability of a component is sufficiently small. As implied in the multiplexing technique, NMR and TMR designs have been used as benchmarks for evaluating fault-tolerant approaches and were implemented in VLSI for high reliability applications [15]. NMR techniques, generally implemented at modular level instead of gate level, use redundant components to mask the effect of faults. In TMR, the most general form of NMR, three identical modules perform the same operation, and a voter accepts outputs from all three modules, producing a majority vote at its output. This majority voter functions as a restoring organ, bringing the outputs to a more reliable level. In this paper, we present a fault-tolerant technique suit- able for an implementation by the manufacturing process of stochastically molecular assembly, the N-tuple interwoven redundancy (NIR) (in particular, the triplicated interwoven redundancy (TIR)). The TIR is presented as a general class of triple modular redundancy (TMR), but implemented with random interconnections. A simulation based reliability model is used to investigate the fault-tolerance of the TIR implemen- tations of a 1-bit processor structure. The TIR is extended to higher orders of NIR, to achieve higher system reliabilities. 0-7695-2128-2/04 $20.00 (C) 2004 IEEE