DESIGNING AND IMPLEMENTATION OF AN ANDROID-BASED PHASOR MEASUREMENT UNIT Chi-Shan Yu Jun-Zhe Yang Department of Digital Design Technology Department of Electrical Engineering National Taipei University of Education, Taiwan I-Shou University, Taiwan chsyu@tea.ntue.edu.tw jzyang@isu.edu.tw ABSTRACT Phasor measurement units (PMUs) have recently been widely studied for smart grid power systems. However, the setup time of a PMU is slow because a conventional phase lock loop (PLL) needs a long settling time to synchronize its first trigger pulse for measuring a synchrophasor. In addition, the user interface of a PMU is poor because most of PMUs have no GUI design. This current work thus presents a new Android-based PMU, which contains a new digital phase lock loop (DPLL) and versatile user interfaces. Using the proposed DPLL, the time synchronous trigger pulses can be rapidly generated from the 1PPS pulses. An Android platform is then designed to receive the time synchronous measurements. To accelerate phasor computations, the discrete Fourier transform (DFT) was directly coded by C language and communicate with Java codes by the Java native interface (JNI). Finally, the proposed PMU was realized on a test system which consists of a DE2 FPGA board, a PIC board, and an ARM-11 6410 board. A simple user interface was also designed on the Android platform for setting and observing some features of the PMU. Hardware evaluations were conducted to prove the effectiveness of the proposed PMU. KEY WORDS Phasor measurement unit, phase lock loop, discrete Fourier transform, Android 1. Introduction The use of PMUs [1] in power systems has become popular in the recent decade. In a smart grid, a PMU is the most important part, which records the three-phase voltage and current phasors for centralized controls and protections. When designing a PMU, time synchronization is critical in measuring wide-area phasors simultaneously. The accurate 1PPS (one-pulse-per-second) pulse provided by Global Positioning System (GPS) is used as a general synchronous time base at each PMU. As a result of the low frequency of the time base, the 1PPS signal cannot be directly used as a trigger pulse for sampling. The phase- lock-loop (PLL) has been widely adopted in PMUs to generate a synchronous high frequency trigger pulse. However, because of the long settling time of a PLL, a conventional PMU needs a very long delay time to accurately follow the 1PPS signal. Sometimes, it takes minutes to measure its first synchrophasor [2]. After synchrophasors have been measured, a PMU still needs to cope with data storages and data communications for a large amount of the measured phasors. Recently, the applications of the Android platform have spread widely from the area of smart phones to general embedded system applications. Android is an open source platform built by Google [3]. The architecture of Android consists of application, application framework, libraries, Android runtime, and Linux kernel. The Android platform can communicate with a specific hardware through the driver on the kernel layer and then it processes the information of such hardware through the user interface on the application layer. The Android platform is very suitable for designing the embedded system of a PMU because of its open-source feature, versatile user interfaces, and highly integrated hardware/software environment. This present work thus realizes the functions of synchronous sampling, phasor computations, data storage, and data communication on an Android platform for a PMU. To accelerate the time synchronous of a PMU, a new DPLL has been proposed. Using the new DPLL, the first accurate synchronous trigger pulse can be generated in one second. Therefore, the drawback of the conventional PLL can be overcome. The proposed PMU was realized and evaluated on a test system, which contains a DE2 FPGA board, a PIC board, and an ARM- 11 6410 board to show the effectiveness. 2. The Proposed PMU 2.1 PMU Configuration In this work, a PMU with an extremely fast DPLL is proposed to measure synchrophasors. The configuration of the PMU is depicted in Fig. 1. The GPS receiver provides the 1PPS signal and the NMEA code [4] sent to the DPLL and the PIC, respectively. The DPLL is realized on a FPGA and the 1PPS signal is utilized to process the frequency multiplication task in the DPLL. The DPLL then provides synchronous trigger pulses to the A/D Proceedings of the IASTED International Conference Power and Energy Systems (AsiaPES 2013) April 10 - 12, 2013 Phuket, Thailand DOI: 10.2316/P.2013.800-082 132