International Journal of Reconfigurable and Embedded Systems (IJRES) Vol. 8, No. 3, November 2019, pp. 194~205 ISSN: 2089-4864, DOI: 10.11591/ijres.v8.i3.pp194-205  194 Journal homepage: http://iaescore.com/journals/index.php/IJRES Performance evaluation of an efficient five input majority gate design in QCA nanotechnology Amanpreet Sandhu, Sheifali Gupta Department of Electronics and Communication Engineering, Chitkara University Institute of Engineering and Technology Chitkara University, India Article Info ABSTRACT Article history: Received Jul 9, 2019 Revised Sep 20, 2019 Accepted Oct 11, 2019 Quantum-dot-cellular-automata (QCA) is the imminent transistor less technology, considered at nano level with high speed of operation and lower power dissipation features. The present paper proposes a novel and an efficient 5-input coplanar majority gate (PMG) with improved structural and energy efficiency. The proposed gate consumes an occupational area of 0.01μm 2 with 17 QCA cells which is 50% less in comparison to the best designs reported in literature. The proposed structure is also more energy efficient because it dissipates 21.1% less energy than the best reported designs. The correctness of a proposed majority gate is verified by designing a single bit full adder. The new 1-bit full adder design is structural efficient and robust in terms of gate count and clock delay. It consumes occupational area of 0.05μm 2 with 58 QCA cells showing 16.6% improvement in structural efficiency as compared to the best design reported in. It is having a gate count of 4 with the delay of 1 clock cycle. Here, the QCADesigner and QCAPro tools are utilized for the simulation and energy dissipation analysis of proposed majority gate and full adder design. Keywords: Full adder Majority gate QCADesigner QCAPro QCA Copyright © 2019 Institute of Advanced Engineering and Science. All rights reserved. Corresponding Author: Amanpreet Sandhu, Department of Electronics and Communication Engineering, Chitkara University Institute of Engineering and Technology Chitkara University, India. Email: amanpreet.sandhu@chitkara.edu.in 1. INTRODUCTION Designing and fabricating complementary metal oxide semiconductor (CMOS) based logic devices at nano scale [1] has an issues like oxide thickness, thermal reliability and power dissipation [2]. Hence the industries are in search of new techniques which could aid the scaling of CMOS. Researchers are well aware that the CMOS technology could be continued only for a decade. Some of the alternate technologies like QCA, single electron tunneling (SET}, carbon nanotubes (CNT) came into existence. QCA is one of the competitive alternate technology [3] that has none of the above said problems. The benefit of QCA devices over regular CMOS circuits are the absence of electron flow for charge transfer and absence of metallic interconnects which are the main source of IR losses with low power consumption [4]. Hence QCA [5] is more prudent than CMOS technology. Many QCA logic designs have been implemented during recent years. Various 5–input majority gates [6-15], 1-bit full adder designs [6-8, 10, 12, 14, 16, 17-29], multiplier designs [30-33], RAM cell structures [34-35], flip flops [36-39] and logic circuits [40, 41]. In the above work, most of the circuits were not potent and hence susceptible to various defects at fabrication level because of the wire-crossing structures of QCA cells. Here, an effective use of cross overs can reduce the number of QCA cells, complexity and total cost. Multiple cross over wire designs results in various fabrication defects [42] and area overhead. One can replace these multilayer structures with 45 degree rotated cells which results in coplanar cross over designs. Such coplanar cross over designs are utilizing two types