15 th International Conference MIXED DESIGN MIXDES 2008 Pozna, POLAND 19 - 21 June 2008 MATS+ TRANSPARENT MEMORY TEST FOR PATTERN SENSITIVE FAULT DETECTION I. MROZEK, V. N. YARMOLIK TECHNICAL UNIVERSITY OF BIALYSTOK, POLAND KEYWORDS: RAM testing, March tests, Pattern sensitive faults ABSTRACT: Conventional memory tests based on only one run have constant and low faults coverage especially for Pattern Sensitive Faults (PSF). To increase faults coverage the multiple run March test algorithms have been used. As have been shown earlier the key element of multiple run March test algorithms are memory backgrounds. Only in a case of optimal set of backgrounds the high fault coverage can be achieved. For such optimal backgrounds the analytical calculation of NPSFk fault coverage for 3 and 4 runs of MATS+ test in this paper is presented. All of the analytical calculations are confirmed and validated by adequate experiments. INTRODUCTION It becomes highly important to test various kinds of defects rapidly and precisely to improve the modern memory quality especially RAM (Random Access Memory) in a SoC (System-on-a-Chip) design environment. The RAM testing is quickly becoming a more difficult issue as the rapidly increasing capacity and density of the RAM chips. Faults modeled from the memory defects can be summarized as follows [1, 2]. Stuck-at-Fault (SF): Either a cell or a line is stuck to logical 0 or 1. Transition Fault (TF): The 0 → 1 (or 1 → 0) transition is impossible on a cell or a line. Coupling Fault (CF): When in a cell is a transition 0 → 1 (or 1 → 0), the content of the other cell is changed. CF is generalized to a k-coupling fault when k − 1 cells are changed and is classified into Inversion or Idempotent coupling faults depending upon what content changed [3]. Retention Faults (RF): A cell fails to retain its logic value after some time. This fault is caused by a broken pull-up resistor. Neighborhood Pattern Sensitive Fault (NPSF): a typical neighborhood pattern sensitive faults preventing the base cell from being transited to a certain value is called ’static’ NPSF, and an NPSF is called ’dynamic’ when a transition on the neighborhood cells triggers a transition on the base cell. The neighborhood pattern sensitive fault (NPSF) model is not new, but it is still widely discussed in the literature of memory testing, and becoming more and more important for memory testing. The problems with testing of semiconductor memories are very different from testing logic. The main reason is that the fault behaviour of memories is inherently analog, while the used fault models have a digital (logical) nature. Traditional March algorithms [1] have been widely used in RAM testing because of their linear time complexity, high fault coverage, and ease in built-in self-test (BIST) implementation. It is known that the traditional March algorithms do not generate all neighborhood patterns that are required for testing the NPSFs, however, they can be modified to get detection abilities for NPSFs. Based on traditional March algorithms different approaches have been proposed to detect NPSFs, such as the tiling method [1, 4], two-group method [1], row-March algorithm [4] and transparent testing [3, 5, 6]. TRANSPARENT MEMORY TESTING March tests are superior in terms of test time and simplicity of hardware implementation and consist of sequences of March elements. The March element in the test includes sequences of read/write (r/w) operations, which are all applied to a given cell, before proceeding to the next cell. The way of moving to the next cell is determined by the address sequence order. During the testing, March tests make use of address sequences called ”up” and ”down” sequences, denoted as ⇑ and ⇓ . The notation  means don’t care the direction of address order. It should be mentioned that the address sequences do not necessarily have to be counting sequences. As an example of the standard memory tests MATS+ test { (w0); ⇑ (r0,w1); ⇓ (r1,w0)} can be considered, which includes just three phases. The first phase is memory initialization (writing all zero background), while the other two phases are sets of read and write operations allow detecting target faults. The MATS+ test detects all stuck-at faults, address faults, some transition faults and some coupling faults, as well as small portion of NPSF [1]. The transparent technique is a well known memory testing approach that retrieves the initial contents of the memory once the test phase has been finished. It is therefore suitable for periodic field testing while allowing preserving the memory content. A transparent BIST is based on a transparent March test that uses the memory initial data to derive the test patterns. The write data can be either the read value or its opposite value. A transparent test algorithm ensures that the last write data is always equals to the first read value in order to satisfy the transparency property. The procedure to derive a transparent test algorithm from a non transparent one (see [6]) can be summarized by the following steps: Copyright © 2008 by Department of Microelectronics & Computer Science, Technical University of Lodz 493