Matthew Morrison, Student Member, IEEE, Matthew Lewandowski, Student Member, IEEE, and Nagarajan Ranganathan, Fellow, IEEE Abstract—Programmable reversible logic is gain wide consideration as a logic design style for modern nanotechnology and quantum computing with minimal impact on circuit heat generation in improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Then, a novel 3*3 programmable UPG gate capable of calculating the universal logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, n-bit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, a novel 4*4 reversible programmable RC gate capable of nine unique logical calculations at low cost and delay is presented and verified. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. These designs are compared to previously existing designs, and their advantages in terms of cost and delay are analyzed. Then, the RMUX is used to improve a reversible SRAM cell we previously presented. The memory cell and comparator are implemented in the design of a Min/Max Comparator device. Index Terms – Comparator; Emerging Technologies; Low Power; Microprocessor; Multiplexer; Reversible Logic; Static RAM I. INTRODUCTION EVERSIBLE logic is a computing design standard where the ideal implementation would produce zero entropy gain [1][13][14][17]. Any reversible logic structure requires an identical number of input and output lines, and is bijective in nature. The three major design goals of reversible logic are as follows. First, minimization of the quantum cost - the number of 1*1 and 2*2 reversible calculations necessary to generate the logical output - will reduce the device’s computational complexity. Second, minimization of the delay - the logical depth of the device – will improve the throughput of the device. Third, reduction of the ancillary inputs and garbage outputs - inputs and outputs not implemented in the design of the gate and only serve to maintain reversibility of the device – will improve the design space require to implement the logic. In Section II, a novel 3*3 programmable UPG gate is proposed and verified that may be utilized in a design requiring a low-cost reversible calculation of AND, NAND, OR, NOR. Next, a novel 5*5 RC gate is presented and verified which may be implemented in an ALU for the calculation of nine logical calculations, and also may be implemented in the design of a comparator. In Section III, the UPG and RC are implemented in the design of novel sequential and tree-based comparators. The designs are verified, and are compared to reversible comparators previously existing in the literature. The advantages of the proposed designs are analyzed in terms of quantum cost and delay. In Section IV, the RMUX is used to improve a reversible SRAM cell we previously presented. The proposed design is verified and compared to the previous design in terms of quantum cost and delay. In Section V, the memory cell and comparator are implemented in the design of a Min/Max Comparator device. II. NOVEL REVERSIBLE LOGIC GATES A. Proposed Swap Gate We propose a reduced implementation of the reversible Swap Gate, which is designed using two integrated qubit gates, and produces a swap of the two input values on the output gate. Previously, the swap gate was implemented using three Feynman gates which produced the outputs   and   , which produces the swap, and incurred a quantum cost and delay of 3. The proposed implementation is accomplished with a quantum cost and delay of 2, was verified using VHDL in Xilinx ISE 12.4, and is shown in Fig. 1. Fig 1: Integrated Qubit Gates Implemented as a Swap Gate Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure R 2012 IEEE Computer Society Annual Symposium on VLSI 978-0-7695-4767-1/12 $26.00 © 2012 IEEE DOI 10.1109/ISVLSI.2012.61 231