A 9.2mW 528/66/50MHz Monolithic Clock Synthesizer for Mobile P Platforms Abstract—A low-power monolithic clock synthesizer suitable for use in mobile P platforms is presented. Clock synthesis is accomplished using an all-Si RF LC reference oscillator that does not require an external frequency reference. Fabricated in 0.18 m CMOS, the developed clock synthesizer demonstrates 1% frequency accuracy over process, voltage, and 0-70 C, exhibits 7.4/21/33ps rms period jitter on 528/66/50MHz clock signals, and achieves a start-up latency of only 3.2 s. I. INTRODUCTION Topics of interest in the area of time and frequency synthe- sis for processor systems include dynamic frequency scaling [1] and external reference (e.g. quartz and ceramic resonators) elimination. When compared to constant frequency operation, dynamic frequency scaling permits a reduction in total system power dissipation. Beyond dynamic frequency scaling, the ability to turn the clock synthesizer OFF and ON with very low latency permits additional power savings. The elimination of external references reduces form factor and can reduce system cost. In this work, it is shown that a RF LC reference oscillator enables low-latency start-up and is well-suited to high-accu- racy monolithic clock synthesis. II. BACKGROUND Of free-running integrated oscillator topologies including LC, phase shift (or RC), ring, and relaxation, LC oscillators exhibit the best short-term frequency stability and lowest fre- quency drift over variations in power supply voltage and tem- perature because unlike the other topologies, the oscillation frequency of an LC oscillator is set by a high-Q harmonic ref- erence. High-frequency phase locked LC oscillators have been the workhorses of frequency synthesis in RF and high-data-rate (over a GHz) digital electronics for years. However, they have only recently been explored as free-running frequency refer- ences for lower-speed and moderate-accuracy digital clock synthesis in applications such as general purpose microcontrol- lers [2] and mobile P platforms, the latter of which is target of this work. In typical clock synthesizers, a low frequency reference oscillator is coupled to a phased-locked loop (PLL) with a large frequency multiplication factor. As shown in [3], such implementations suffer from high jitter due to noise accumula- tion inherent to frequency multiplication. In contrast, a high frequency reference oscillator permits frequency division which reduces jitter by the same factor in which it is accumu- lated in the PLL approach. Thus, an RF LC reference oscillator, with even a modest division ratio, can be utilized to develop very low jitter clock signals. In the RF LC reference oscillator approach, the primary design challenge becomes maintaining high frequency-accuracy over variations in process, power sup- ply voltage, temperature. Fig. 1a shows the schematic a generalized negative- transconductance (-g m ) LC oscillator with finite amplifier out- put impedance and parasitic inductor and capacitor implemen- tation losses. Ignoring all of the loss in the system, the natural frequency of the system is . However, consid- ering the parasitic losses in the tank, R L and R C , the natural fre- quency of the system, which must be redetermined by solving for the zero phase of the lossy LC network, becomes: (1) In monolithic LC oscillators, R L is usually substantially larger than R C ; thus, (1) can be reduced to the following: (2) o 1 LC = Fig. 1. (a) Generalized schematic of a -g m LC oscillator with a lossy integrated L and C as well as a finite -g m amplifier output resistance. (b) As g m0 is increased, the harmonic content of i(t) increases as the waveform becomes more square. (c) The injected current is absorbed by the capacitor on each half- cycle distorting i c (t) and ultimately v(t) and the oscillation frequency (f o ). -g m + _ + _ R L L C v + _ R C i R o R o i c t g m0 i(t) t i c (t) (a) (b) (c) o 1 LC ------- CR L 2 L – CR C 2 L – ------------------- = o 1 LC ------- 1 CR L 2 L ---------- – = M. S. McCorquodale, S. M. Pernia, J. D. O’Day, G. Carichner, and S. Kubba Mobius Microsystems, Inc. Detroit, MI 48226-1686 USA {mccorquodale, pernia, oday , carichner, kubba}@mobiusmicro.com 15-6-1 IEEE 2005 CUSTOM INTEGRATED CIRCUITS CONFERENCE 0-7803-9023-7/05/$20.00 ©2005 IEEE. 523