Copyright © 2018 Authors. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited. International Journal of Engineering & Technology, 7 (2.23) (2018) 464-466 International Journal of Engineering & Technology Website: www.sciencepubco.com/index.php/IJET Research paper Design of ASIC Square Calculator Using AncientVedic Mathematics Angshuman Khan 1* , Sudip Halder 2 , Shubhajit Pal 3 1 Dept. Of Electronics & Communication Engineering, University Of Engineering & Management, Jaipur, India 2,3 Dept. Of Electrical Engineering, University Of Engineering & Management, Jaipur, India *Corresponding Author E-Mail:Angshumankhan2910@Gmail.Com Abstract This article includes a simple design of Vedic square calculator for Application Specific Integrated Circuit (ASIC). This is a straightfor- ward and innovative design of Vedic calculator using only few basic digital logic gates. Among the all sutras and sub sutras of ancient Vedic mathematics, the sutra „Urdhva Tiryagbyham‟ is used here for square calculation of two bits numbers which results in an effortless and faster method of square calculation than all the existing methods. The design and minimization of the circuit has been carried out to achieve a standard architecture that is the simplest too. Here Xilinx ISE software tool is used rigorously to simulate the architecture. Keywords: Multiplier; Square calculator; Urdhva Tiryagbyham; Vedic mathematics. 1. Introduction Multiplication is a basic mathematical operation for all processors. The squaring means self multiplication, i.e. multiplicand and mul- tiplier are same. Lots of popular Vedic multipliers with verities of advantages and disadvantages are available and fascinated the interest of researchers. Thus designing a self multiplier or square calculator or squarer is of course a noteworthy attempt. In this article the ancient Vedic mathematics formula is used purposefully for the enhancement of calculation speed. Many popular existing multipliers are there for different applica- tions, like the digital processor‟s multipliers, named DSP multipli- er [1]. A reduced bit UT-multiplier proposed in 2008 [2]. The array multiplier and UT-multiplier up to four bits discussed earlier [3]. A good approach of 64 bits squarer is projected already [4]. In 1951, the multiplication method of signed binary numbers has been discussed [5]. 32 bits multiplier for faster operation has been considered previously [6]. In 2004 the architecture of Overlay multiplier has already been taken care of [8]. EDA tool multiplier is also there in research of multipliers [9]. Several hardware im- plementations of different multipliers using Vedic concepts have also been anticipated. Area efficient NND multiplier using Vedic sutras have been implemented [10]. A comparison of hardware based conventional multipliers vs. Vedic multipliers is done [11]. A 32×32 bits multiplier and it‟s hardware implementation is done formerly [12]. Factorial calculator is also implemented earlier [13]. The matrix multiplier has already haggard the attention of the experimenter [14]. The multiplier model to multiply special numbers is also noteworthy here [15-16]. But among all discussed multipliers, the recent ASIC square calculator is well accepted [17]. A new modified architecture of recently proposed multiplier [17], which is the simplest and minimized one for square calculation, is designed here for Application Specific Integrated Circuit (ASIC). But the design proposed here includes only a few number of fun- damental digital logic gates by successfully applying the concept of Vedic formula. In all probability this type of Vedic square cal- culator has not been implemented before. Popular ISE Xilinx software tool has been used for the confirmation of the proposed architecture. 2. Vedic Mathematics Swami Bharati Krishna Tirtha (1884-1960), former Jagadguru Shankarachraya Maharaj selected a set of sixteen Sutras and thir- teen Sub Sutras from „Atharva Veda‟ [7]. Vedic mathematics is an „Upa Veda‟ of „Atharva Veda‟. Vedic mathematics is advanta- geous in reducing the complexity of conventional methods and turns into simpler calculation technique. As the formulas and sub formulas resembles very closely the human brain functions, this is a very appealing field, not only for mathematicians but also for engineers [5]. The sutra „Urdhva Tiryagbyham‟ („UT‟) is used here to implement the proposed squarer. The sutra means „verti- cally and crosswise‟ operations. Calculations become simpler by applying this formula in multiplication techniques [7]. The multi- plication method using „UT‟ sutra leads to lesser steps, space, and further reduces the calculation burden. The sutra has been effi- ciently used in this article. 3. Proposed Design Two bits multiplier and two bits multiplicand numbers are multi- plied here. The procedure of multiplication is discussed below. At first the least significant bits (LSBs) are multiplied (vertical) i.e. both the LSBs of multiplier and multiplicand is multiplied first to get least significant bit (LSB) of the resultant product.