Implementation and Analysis of an Error Detection and Correction System on FPGA Constantin Anton, Laurenţiu Mihai Ionescu, Ion Tutănescu, Alin Mazăre, Gheorghe Şerban University of Piteşti, Romania Abstract This paper presents a solution to design and implement a hardware error detection and correction circuit using associative memories. This type of memory allows search of a binary value stored, having input data a partial (or modified) amount of this value. This property can be used in communication, for detection and correction of errors. In our analysis, the obtained experimental results were compared with performances of other hardware systems. 1. Introduction Usage of error correcting control is very important in the modern communication system. BCH codes (Bose, Chaudhuri, and Hocquenghem) are widely used in communication networks, computer networks, satellite communication, magnetic and optic storage systems. This paper presents the prototyping of a BCH encoder and decoder using associative memory. BCH codes operate over finite fields or Galois fields. BCH codes can be defined by two parameters that are: length of code words, n, and the number of errors to be corrected, t. The BCH codes are a class of cycle codes whose generator polynomial is the product of distinct minimal polynomials, corresponding to α, α 2 , … , α 2t , where   m GF 2   is a root of the primitive polynomial g(x)[1]. An irreducible polynomial g(x) of degree m is said to be primitive if only if it divides polynomial form of degree n, 1  n x for no n less than 1 2  m . In fact, every binary primitive polynomial g(x) of degree m is a factor of 1 1 2   m x [2]. For our application we use generator polynomial: 1 ) ( 2 4 5 8 10        x x x x x x x g . which can correct 3 erroneous bits and detect 6 errors. 2. Hardware circuits for errors detection and correction Field-Programmable Gate Arrays (FPGAs) have become one of the key digital circuit implementation media over the last decade [3]. One bit patterns will produce operational circuits and can be used in many areas, like that of communication systems. Our hardware scheme is based on polynomial generator for errors detection and correction. FPGA circuits represent a compromise between circuits with microprocessor and ASIC circuits (Application Specific Integrated Circuits) [4]. First, they present flexibility in programming, called here reconfiguration, which is a feature for microprocessors. Even if FPGA cannot be programmable while operation, they can be configured anytime is needed, having a structure based on RAM programmable machines. On the other hand, they allow the parallel structures implementation, with smaller response times than a system with microprocessor. FPGA is organized as a 2D array of configurable logic blocks (CLB). They can be interconnected via global bus, which is realized between configurable blocks, or by local bus, which is realized within a CLB. In turn, each CLB circuit has a total of 4 slices. A slice contains a logic functions generator (can implement any logic function with 4 inputs and one output), an arithmetic logic, flip-flops and multiplexers to connect with other neighboring slices. Because this architecture, FPGA circuits are especially useful in applications that rely on network logic cells. Associative memory is a type of memory that can be addressable by the content. Instead to know an address, to access a location is sufficient to know the content part of the location. Using partial content is a search until it finds the memory location it contains. Thus, it is partially associated content (data entry) with full content value (found at that location). There are many works that have used FPGA circuits to detect and correct errors. This is because these devices are affordable and can be purchased at low prices. Also, development tools for these circuits are available. So they were made in FPGA implementation of algorithms for calculating the checksum (CRC) and automatically attach it to the packet that is transmitted on the communication channel [5], implementation of BCH error correction codes [6], implementation of SR-ARQ hybrid algorithms [7], algorithms for checking parity checksum type [8] and the class of quasi-cyclic LDPC codes [9]. In all these examples, we have machines that perform calculations implemented in FPGA. International Journal of Intelligent Computing Research (IJICR), Volume 3, Issues 3/4, Sep/Dec 2012 Copyright © 2012, Infonomics Society 348