JOURNAL OF ELECTRONIC TESTING: Theory and Applications 16, 147–155 (2000) c  2000 Kluwer Academic Publishers. Manufactured in The Netherlands. Oscillation Ring Delay Test for High Performance Microprocessors WEN CHING WU, CHUNG LEN LEE AND MING SHAE WU Department of Electronics Engineering, National Chiao Tung University, Hsin Chu, Taiwan, ROC cllee@cc.nctu.edu.tw JWU E. CHEN Department of Electrical Engineering, Chung Hwa University, Hsin Chu, Taiwan, ROC MAGDY S. ABADIR Somerset Design Center, Motorola Inc., Austin, TX, USA Received January 15, 1999; Revised July 6, 1999 Editor: A.P. Ambler Abstract. This paper proposes a new test scheme, oscillation ring test, and its associated test circuit organization for delay fault testing for high performance microprocessors. For this test scheme, the outputs of the circuit under test are connected to its inputs to form oscillation rings and test vectors which sensitize circuit paths are sought to make the rings oscillate. High speed transition counters or oscillation detectors can then be used to detect whether the circuit is working normally or not. The sensitizable paths of oscillation rings cover all circuit lines, detecting all gate delay faults, a large part of hazard free robust path delay faults and all the stuck-at faults. It has the advantage of testing the circuit at the working speed of the circuit. Also, with some modification, the scheme can also be used to measure the maximum speed of the circuit. The scheme needs minimal simple added hardware, thus ideal for testing, embedded circuits and microprocessors. Keywords: oscillation ring testing, delay fault testing, sensitized path, gate delay fault, robust path dealy fault, stuck at fault, hazard-free path delay fault, multiple reconvergent fanout, flunk lines 1. Introduction Testing digital logic circuits, especially for high per- formance microprocessors which work at a high speed, is a difficult and expensive task. Due to the difficulty, most testing primarily focuses on stuck-at faults. How- ever, with the increasing performance and complexity of logic circuits, stuck-at fault testing becomes insuffi- cient to guarantee an acceptable quality level of proper system operation. Delay fault testing is one of possible exercises to improve the testing efficiency to guaran- tee the logic circuit quality. There is much research on delay fault testing [1–14]. For example, the fault mod- els treated include gate delay fault models, path de- lay faults, robust delay faults, non-robust delay faults, and hazard-free delay faults [4–14]. However, for all the approaches treated, the testing setup is rather com- plicated, i.e., it needs two sets of latches, each with a separately precisely controllable clockings to apply the initialization-excitation test pattern pairs and read out test result respectively [4]. In addition, to implement the above delay testing schemes to microprocessors, a scan design for testability needs to be incorporated to shift patterns into and out of the circuit, making the