14 Electronics COOLING | September 2014 INTRODUCTION 3 D INTEGRATION is consid- ered a promising packag- ing technology option to increase transistor density by vertically integrating two or more dice with a dense high-speed interface with shorter interconnect length, enabling a smaller package form factor across a variety of market segments [1-2]. How- ever, despite its promising electrical benefits, effective cooling of 3D stacked die packages remains a challenge [3-5], which could impact the long-term reli- ability of active devices in the package. In order to better understand and quantify the thermal response of 3D stacked die packages, accurate char- acterization of thermal behavior and establishment of appropriate thermal design rules for the feasibility of various integration options are essential. In the previous article by the current authors [6], a thermal analysis meth- odology was presented for predicting cooling capabilities of Multi-Chip Package (MCP) architectures with multiple side-by-side dice. e thermal analysis methodology is based on the principle of linear superposition in conduction heat transfer to calculate the die junction temperatures at an ar- bitrary combination of powers applied to the dice under steady-state condi- tions [7-8]. In this article, the thermal analysis methodology is extended to predicting cooling capabilities of MCP architectures with 3D stacked dice. Estimating the Thermal Interaction between Vertically Stacked Chips in a Multi-Chip Package Je-Young Chang, Ashish Gupta Intel Corporation Calculation Corner Je-Young Chang received his B.S. and M.S. degrees from the Seoul National University in South Korea and his Ph.D. degree from University of Texas at Arlington, all in mechanical engineering. He worked at Penn State University for three years as a research associate before joining Intel in 2000. He has worked on many aspects of advanced cooling technologies, including two- phase immersion cooling, single/two-phase microchannel cooling, corrosion reliability of liquid cooling systems, heat pipes, TIMs, heat exchangers, etc. He has 19 issued/pending US patents, and more than 60 articles in archival journals, conference proceedings and Intel internal publications. Ashish Gupta manages the Thermals/Fluids Core Competency Team in Intel’s Assembly and Test Technology Development Group in Arizona. He holds a Ph.D. degree in Mechanical Engineering from Purdue University. His group is responsible for the R&D of advanced package thermal and cooling technologies, modeling methodologies and metrologies for Intel’s current and future generations of processors for product segments during the discovery, definition, development and certification stages of technology maturity. The team‘s scope covers the entire gambit of Intel product segments across all market segments ranging from handheld devices and small form factor packages to higher power server products. FIGURE 1: Schematic of speculative MCP with 3D die stack (Not drawn to scale).