IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 43, NO. 9, SEPTEMBER 2008 2109 A Stable 2-Port SRAM Cell Design Against Simultaneously Read/Write-Disturbed Accesses Toshikazu Suzuki, Hiroyuki Yamauchi, Member, IEEE, Yoshinobu Yamagami, Katsuji Satomi, and Hironori Akamatsu Abstract—A 2-port SRAM cell has to guarantee stability against simultaneously read and write (R/W)-disturbed accesses while keeping cell current (Icell). We verified that it was difficult to provide the stability without any decrease in Icell and any increase in the cell-area penalty only by using the previously proposed techniques for a 1-port cell, and have proposed a new cell biasing technique that controlled the level of the cell VSS (VSSM) with a dual-Vdd and a reduced write-bit-line (WBL) precharge scheme for an 8-transistor (8T) 2-port cell to address the above issue. In this paper, a further consideration was newly demonstrated about the stability for a 2-port SRAM under the random fluctu- ation of the threshold-voltage (Vth) in 65-nm CMOS technology. The stability with the proposed biasing was compared with that of the conventional cell-Vdd (VDDM) control for write assist [5], [6]. The results under 4- random-Vth fluctuation verified that the minimum Icell at a simultaneously R/W-disturbed cell increased by 2.4 times at Vdd while improving the write margin (WRTM). The cell size based on the same Icell was re- duced by 20%. The minimum static noise margin (SNM) was also improved by 44%. Each stability also had the tolerance against 6- random-Vth fluctuation. Furthermore, we have challenged to apply the proposed cell biasing to a 7-transistor (7T) 2-port cell design for area saving with a unique write-assist scheme. The cell size was reduced by 26% with the 7T cell compared with that of the conventional 8T cell. This proposed cell biasing satisfied all the requirements of 2-port SRAM operation while improving stability and saving cell size. Index Terms—Cell-current, embedded SRAM, memory cell, sta- bility, 2-port. I. INTRODUCTION M ANY discussions have been held about the stability for an SRAM cell in recent years [3]–[8] against the re- duction in the cell-operating margin due to the device fluctua- tion with scaling after 65-nm technology node. The useful assist techniques were reported so far to improve the cell-operating margins, such as the new cell topology [3], [4] and the cell-bias control [5]–[8]. However, those discussions were mainly based on the assist technique for a 1-port SRAM cell which is inde- pendently read or write accessed at a time. Manuscript received December 16, 2007; revised May 19, 2008. Current version published September 10, 2008. This work was supported in part by a Grant-in-aid for scientific research from the Information Science Laboratory of Fukuoka Institute of Technology. T. Suzuki, Y. Yamagami, K. Satomi, and H. Akamatsu are with the System LSI Technology Development Center, Semiconductor Company, Matsushita Electric Industrial Co., Ltd., Kyoto 617-8520, Japan (e-mail: suzuki.san@jp.panasonic.com). H. Yamauchi is with the Faculty of Information Engineering, Department of Computer Science and Engineering, Fukuoka Institute of Technology, Fukuoka 811-0295, Japan.. Digital Object Identifier 10.1109/JSSC.2008.2001872 As for a 2-port SRAM which is widely used for an interface between the macro-blocks in SoC, a simultaneous R/W access has to be guaranteed with keeping enough Icell even though it is accessed in a same column. This guarantee obligation makes it much more difficult for a 2-port cell design compared with that of a 1-port cell to realize a simultaneous static noise margin (SNM), WRTM and Icell. We verified that the conventional operating-margin assist techniques proposed so far for 1-port SRAM have not satisfied a 2-port SRAM operation simultaneously as shown in Table I [1], [2]. And we have proposed a new cell-biasing scheme which controlled VSSM for the write assist with a dual Vdd and a reduced write-bit line (WBL) precharge scheme to enhance SNM. This proposed biasing scheme met all the requirements for a 2-port SRAM operation without any decrease in Icell. In this paper, a further consideration was newly demonstrated about the stability for a 2-port SRAM under the random fluctu- ation of Vth in 65-nm CMOS technology. The cell-operating margins under 4- random-Vth fluctuation that corresponds to a 32-Kbit memory capacitance were verified. And their toler- ance against 6- random-Vth fluctuation was also estimated. Moreover, we have challenged to apply the proposed biasing to a 7T 2-port cell design for area saving with a unique write-as- sist scheme. The proposed biasing scheme was implemented in a 32-Kbit 2-port SRAM with a 65-nm LSTP CMOS, and it demonstrated that: 1) the minimum Icell at a simultaneously R/W-disturbed cell was increased by 2.4 times while improving WRTM, and thereby the cell size based on the same Icell was re- duced by 20%, 2) the minimum SNM at a half-selected cell was improved by 44%, and 3) the proposed 7T 2-port cell saved the cell size by 26% without any decrease in cell current, each com- pared with the conventional VDDM control technique [5], [6] under 4- random-Vth fluctuation at Vdd . Each oper- ating margin also had the tolerance against the 6- random-Vth fluctuation. This paper is organized as follows. Following the discussions on the requirements for the 2-port operation, the proposed cell- terminal biasing scheme for 8T 2-port cell and the simulated re- sults are described in Section II. Another area-saving 7T 2-port cell design was demonstrated in Section III. After showing the implementation results of a 32-Kbit SRAM in Section IV, the conclusions were given in Section V. II. CELL-BIASING SCHEME FOR 2-PORT SRAM A. Issues in Conventional Cell-Stability Assist The several memory-cell topologies [3], [4] and the cell- terminal bias controls [5]–[8] for a 1-port SRAM have been 0018-9200/$25.00 © 2008 IEEE