IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 31, NO. 9, SEPTEMBER 1996 1285 A Signal-Swing Suppressing Strategy for Power and Layout Area Savings Using Time-Multiplexed Differential Data-Transfer Scheme Hiroyuki Yamauchi and Akira Matsuzawa, zyxwvu Member, IEEE zyxwv Abstruct- This paper presents a signal-swing suppression strategy which uses a time-multiplexed differential data-transfer (TMD) scheme combined with a data-transition detector (DTD) circuit, featuring shared complementary wires, which are originally allocated to adjacent signal bits, respectively. TMD can be exploited to reduce the signal voltage-swing and to realize a charge-recycling bus (CRB) architecture zyxwvutsrq [l]. This enables a dramatic power reduction without the throughput-loss due to time-multiplexing, while maintaining the same number of signal wires compared to a single signal line (SSL) scheme. This is because the differential transfer scheme inherently has a more capability in terms of throughput and noise tolerance compared to SSL. To demonstrate the effectiveness of TMD with DTD and TMD with CRB (TM-CRB), power consumption comparisons were made between SSL, the parallel architecture [2], TMD with DTD, and TM-CRB. For all measurements, the same throughput conditions were used based on the simulated and measured data of the 0.5 pm CMOS devices. This paper presents why TM-CRB can reduce the power dissipation on heavily loaded bus lines to less than 1/31 and 1/8, with the bus activity of 100% and 25%, respectively, while maintaining the same number of signal wires, compared to SSL. I. INTRODUCTION N recent years, the parallel architecture [2] has become the I centerpiece of low-power techniques. This is because the parallel architecture can be exploited to scale the power-supply voltage, enabling quadratic power reduction while maintaining the same throughput. The parallel architecture was used in the data path circuits which include logic gates, such as adder, comparator, latch, etc. [2]. However, the method of power savings by using the par- allel architecture has the overhead of increased layout area and would not be suitable for area-constrained designs. For example, when exploiting the parallel architecture in designing the data-bus circuits for interconnecting the embedded memory and the graphics controller [as shown in Fig. l(a)], there inevitably comes an increase in the number of signal wires to recoup the throughput-loss due to the scaled supply voltage and the lower operating frequency. This problem becomes more serious as the supply voltage approaches the sum of the threshold voltage. This is because the speed-degradation due to the reduced supply voltage will be intolerably increased (eventually, it will be exponentially increased). Manuscript received September 5, 1995; revised March 12, 1996. The authors are with the Semiconductor Research Center SL23, Matsushita Publisher Item Identifier S OOlS-9200(96)06474-8. Electric Industrial Co., Ltd., Osaka, Japan. Memory Graphics-Controller zyx & Data-Rate = Fra*N 555 Power Data-Rate Cbus Vbus Vcc (4 HDTV 3D-Graahics (Game) HDTV 3D-Graphics (Game) 6 mm 1.6Gbls 25.6GbIs zyxw of N-bits Bus Width zyxwvu N (bit) (c) Fig. 1. (a) Background for low-power bus architecture. (b) Target on bus-power consumption for this work. (c) Percentage of wiring area versus the number of wirings. On the other hand, the differential data transfer scheme, which is almost used in the memory circuits, including DRAM [3] and SRAM, is clearly a very effective way to reduce the bus power consumption on heavily loaded data lines. This is because the differential data transfer scheme inherently has higher noise margin and can reduce the signal voltage- swing when compared against single signal line (SSL) scheme 0018-9200/96$05.00 zyxwvutsr 0 1996 IEEE