1104 IEEE JOURNAL OF SOLID-STATE CIRCUITS, VOL. 23. NO. 5, OCTOBER 1988 A 16-Mbit DRAM with a Relaxed Sense-Amplifier-Pitch Open-Bit- Line Architecture MICHIHIRO INOUE, TOSHIO YAMADA, HISAKAZU KOTAN1, HIROYUKI YAMAUCHI, ATSUSHI FUJIWARA, JUNKO MATSUSHITA, HIRC~NORI AKAMATSU, MASANORI FUKUMOTO, MASAFUMI KUBOTA, ICHIRO NAKAO, NOBUO AOI, GENSHU FUSE, SHIN-ICHI OGAWA, SHINJI ODANAKA, ATSUSHI UENO, AND HIROSHI YAMAMOTO Abstract —A 16-Mbit dynamic RAM has been designed and fabricated rising 0.5- pm CMOS technology with double-level metaflization. It uses a novel trench-type surrounding high-capacitance cell (SCC) that measures only 3.3 p r# in cell size with a 63-fF storage capacitance. A novel relaxed sense-amplifier-pitch (RSAP) open-bit-line architecture used on the DRAM achieves high-density memory cell array, while maintaining a large enough layout pitch for the sense amplifier. These concepts allow the small chip that measures 5.4 X 17.38 (93.85) ma? to be mounted in a 300-mil dual- in-line package with 65-ns RA S access time and a 35-ns column address access time. I. INTRODUCTION W ITH THE advancement of the 16-Mbit DRAM generation, the component count has been in- creased by a factor of 4 over the 4-Mbit generation. However, to keep the same packing density, these DRAM chips should be assembled in 300- or 350-mil-wide packages. In order to mount 16-Mbit DRAM in 300- or 350-mil-wide packages, the die size has to be smaller than 100 mmz and the memory cell size has to be smaller than 4 pm2 with a capacitance large enough for alpha-particle- induced soft-error tolerance and the stable sense operation. The folded-bit-line architecture (true folded bit line) has been generally used for 64-kbit through 4-Mbit DRAMs to improve the noise immunity and provide larger layout pitches for the sense amplifiers. However, in the case of a 16-Mbit DRAM which will be fabricated with 0.5- or 0.6-pm design rules, it is difficult to design a chip which possesses four times the component count of a 4-Mbit DRAM by only design-rule reduction and cell structure improvement. After all, it further requires the improved memory array architecture to achieve the 16-Mbh DRAM. The open-bit-line architecture basically provides for a smaller geometry memory cell over the folded-bit-line ar- chitecture [1]. However, in the case of the conventional open-bit-line architecture, there are problems such as 1) the requirement of smaller layout pitch for the sense amplifier than for the folded-bit-line architecture, and 2) degradation of the coupling noise immunity. The novel relaxed sense-amplifier-pitch open-bit-line ar- chitecture [2] is adopted on this 16-Mbit DRAM in order to overcome these problems. Although memory cells are arranged at all the crosspoints of the word lines and the bit lines, the pitch of the sense amplifier is equal to double the pitch of the bit lines. The memory array has been realized using a novel surrounding high-capacitance trench cell structure [3], [4] adaptive open-bit-line architecture. This paper describes a 0.5-pm minimum design rule, CMOS 16-Mbit DRAM using this architecture and mem- ory cell structure. In Section II the memory cell structure is described. In Section III the basic memory array architec- ture is discussed. In Section IV the DRAM chip design and its performance are described. II. MEMORY CELL STRUCTURE Several kinds of trench cell structures have been pro- posed for large-scale DRAMs such as 4-Mbit and 16-Mbit capacities [5]–[15]. These trench cell structures are divided into three types. The first structure is the inner storage-node trench cell which stores the information charge in the polysilicon node being formed inside the trench [5]-[7]. The second type is the isolation-merged trench cell which uses the whole or partial area of the transistor-to-transistor isolation for the storage capacitor [8]–[1 1]. The third type is the double-trench structure which has two polysilicon layers for the storage node and the cell plate in the trench [12] -[15]. Manuscript received A ril 5, 1988; revised June 20, 1988. In the case of the inner storage-node trench cell, a t% The authors are with e Semiconductor Research Center, Matsushita disadvantage is that a half-v== plate method cannot be Electric Industrial Company, Ltd., 3-15, Yagumo-N&amachi, Moriguchi, Osaka 570, Japan. used because the cell plate is the substrate. The double- IEEE Log Number 8823138. trench structure eliminates this problem since another