Design of 1 V Operating Fully Differential OTA Using NMOS Inverters Atsushi Tanaka 1 and Hiroshi Tanimoto 2 1,2 Department of Electrical and Electronic Engineering, Kitami Institute of Technology 165 Koen-cho, Kitami-shi 090-8507, Japan E-mail : 1 mel07012@std.kitami-it.ac.jp, 2 tanimoto@elec.kitami-it.ac.jp Abstract: A 1 V operating fully differential OTA is pre- sented. We designed a 1 V operating fully differential OTA using NMOS inverters in place of traditional differential pair. To obtain high voltage gain, a two stage configuration has been used in which the first stage has feedforward to can- cel common-mode signal and the second stage has common- mode feedback. This OTA was fabricated by 0.18 μm CMOS technology. Measured dc gain is 40 dB and a unity gain fre- quency is 10 MHz. This OTA leads a solution to the low supply voltage issue in scaled CMOS analog circuits. 1. Introduction The operation of analog circuits from low supply voltages be- comes necessary due to down scaling of technologies. In the near future, the operation of analog circuits from 1 V sup- ply voltage will be indispensable (Figure 1 [1]). However, it is difficult for traditional fully differential OTA using differ- ential pair to operate from 1 V supply voltage. There is an idea using CMOS inverters in place of the differential pair to lower its operating voltage [2], [3], however, CMOS inverters require at least 2V th so that the low supply voltage operation below 1 V may be difficult. 2005 2010 2015 2020 2025 0 0.2 0.4 0.6 0.8 1 1.2 Year Supply Voltage [V] High-performace Low Standby Power 25 nm 20 nm 16 nm 13 nm 10 nm 8 nm 6.3 nm 5 nm Figure 1. Supply voltage trend (ITRS road map) On the other hand, it is possible for NMOS inverters to operate from lower supply voltages than CMOS inverters. A 0.9 V operating fully differential OTA using NMOS inverters have been reported [4]. However, the OTA cannot control its common-mode output voltages by itself, because it has only feedforward paths to cancel common-mode signals. On the other hand, the cascade connection of feedforward OTA and feedback OTA (F/F+F/B OTA) structure [3] can control its common-mode output voltages at the half of supply voltage by common-mode feedback. We designed and fabricated a 1 V operating fully differential OTA using NMOS inverters in place of CMOS inverters in F/F+F/B OTA . Simulated and measured results are presented. 2. Issues in Low Supply Voltage Operation A traditional fully differential OTA uses the differential pair. The differential pair is shown in Figure 2. This construc- tion has more than three stacked MOSFETs between V DD and GND, so that it is difficult for the differential pair to operate from supply voltages as low as 1 V. To overcome this sit- uation, we must adopt circuits with less number of stacked transistors. M p2 V out+ V in+ M n3 V bias1 V bias2 V DD V out- V in- M n1 M n2 M p1 2V DSn(sat) V DSp(sat) V out V in 2V DSn(sat) +V thn V DD GND GND Figure 2. Differential pair There has been some ideas using CMOS inverters in place of the differential pair to lower its operating voltage[2], [3]. The CMOS inverter is shown in Figure 3. This configura- tion has only two stacked MOSFETs between V DD and GND. However, CMOS inverters still require at least 2V th to operate so that the operation below 1 V may be difficult. It is possible to lower the threshold voltage V th by using additional process steps; however, it is not practical from the view point of increased production cost and leak currents in the digital circuit. Thus, we decided to adopt simple NMOS inverters, instead of CMOS inverters. The NMOS inverter is shown in Figure 4. The use of a PMOS as a load current source makes it possible to deter- mine the NMOS inverter’s bias current independent of the V th of NMOS. Therefore, it is possible for NMOS inverters to operate from lower supply voltages than CMOS inverters. 3. OTA Design A circuit configuration of the F/F+F/B OTA is shown in Fig- ure 5 [3]. This OTA consists a fully differential two-stage OTA, in order to obtain high gain. We could obtain only about 20∼30 dB of voltage gain, if we used a single stage construc- tion because of low output impedance of 0.18 μm CMOS pro- cess for the minimum gate length. The 23rd International Technical Conference on Circuits/Systems, Computers and Communications (ITC-CSCC 2008) 417