Materials Science in Semiconductor Processing 8 (2005) 343–346 Strained-Si n-MOS surface-channel and buried Si 0.7 Ge 0.3 compressively-strained p-MOS fabricated in a 0.25 mm heterostructure CMOS process D.J. Paul a,Ã,1 , M. Temple a,1 , S.H. Olsen b , A.G. ONeill b , Y.T. Tang c , A.M. Waite c , C. Cerrina c , A.G.R. Evans c , X. Li d , J. Zhang d , D.J. Norris e , A.G. Cullis e a Cavendish Laboratory, University of Cambridge, Madingley Road, Cambridge CB3 0HE, UK b School of Electrical, Electronic and Computer Engineering, Newcastle University, Newcastle NE1 7RU, UK c Department of Electronics and Computer Science, Southampton University, Southampton SO17 1BJ, UK d Blackett Laboratory, Imperial College of Science, Technology and Medicine, Prince Consort Road, London SW7 2BZ, UK e Department of Electronics and Electrical Engineering, University of Sheffield, Mappin Street, Sheffield S1 3JD, UK Abstract A 0.25 mm complimentary metal oxide semiconductor (CMOS) process has been used to fabricate surface channel strained-Si n-MOS devices and buried, compressively-strained-Si 0.7 Ge 0.3 channel p-MOS. Enhancements in performance of on-current, transconductance and mobility over bulk, relaxed Si CMOS devices are demonstrated for both n- and p-MOS devices for all gate lengths fabricated from 0.1 up to 10 mm. The performance is compared to surface channel strained-Si CMOS which is superior to the buried channel results. Possible reasons are discussed. r 2004 Elsevier Ltd. All rights reserved. PACS: 72.20.Fr; 73.20.Dx; 73.40.Qv Keywords: CMOS; Strained-Si; SiGe 1. Introduction One of the major problems of the downscaling of complementary metal oxide semiconductor (CMOS) microelectronics is the reduction in the mobility of inversion layer carriers as the gate oxide thickness is reduced significantly below about 3nm [1]. To counter the degregation, strained-Si CMOS technology has been proposed as one scheme to enhance the mobility of the carriers to improve the device performance [2,3]. While large enhancements in the n-channel mobilities and device performance has been demonstrated, the hole enhancements have been significantly lower [4]. A number of different authors have proposed the integration of a buried, compressively strained Si 1x Ge x channel which has the potential for higher p-channel mobility than surface channels [2] through the reduced effective masses and interface roughness scattering. Circuit and device simulations suggest that a strained- Si surface channel combined with the buried p-channel device would be the best solution to many typical digital logic circuit designs as this maximises the n-channel enhancements while providing a higher enhancement in ARTICLE IN PRESS 1369-8001/$-see front matter r 2004 Elsevier Ltd. All rights reserved. doi:10.1016/j.mssp.2004.09.106 Ã Corresponding author. E-mail address: dp109@cam.ac.uk (D.J. Paul). 1 The work was funded by EPSRC under the HMOS II programme.