Proceedings of the 2006 Winter Simulation Conference L. F. Perrone, F. P. Wieland, J. Liu, B. G. Lawson, D. M. Nicol, and R. M. Fujimoto, eds. ABSTRACT Intel’s Fab-18 is based in Israel, and has transitioned from producing 0.18-micron logic devices to producing 90nM flash products. During this transition period, the factory has de-ramped in volume of logic while ramping-up flash. AutoSched AP software was utilized for the development of a transient simulation model of the Fab’s behavior dur- ing this period. It is the first attempt, at Intel, to utilize a full factory simulation in order to analyze and support de- cisions that pertain to a transient period of parallel de-ramp and ramp-up of technologies. Unlike typical simulation models for the analysis of factory performance and behav- ior in steady-state, the transient model poses several mod- eling challenges and requires major adjustments in dealing with these challenges. In this paper, we discuss those as- pects. The benefits and contribution of such a model to de- cision making and the improvement of factory perform- ance are also presented. 1 BACKGROUND A semiconductor manufacturing process is a complex manufacturing process. It typically consists of hundreds of production stages (or process steps), performed by dozens of different tool types, on a highly reentrant process flow and with various technology and operational restrictions such as queue time and layers/tools restrictions, over a high mixture of products processed simultaneously. Given the stochastic nature of the process, resulting from the variability in processing times and, primarily, the relatively significant portions of downtime of the tools per- forming the process steps, it should come as no surprise that simulation models have been used over the years to investigate the environments of semiconductor manufac- turing. However, these models have been extensively utilized to evaluate the effects and behavior of various operating environments during steady-state. Specific examples of steady-state simulations used in semiconductor manufac- turing can be found in Allen et al. (1999) or DeJong and Fischbein (2000). Kalir and Avidan (2001) developed a simulation for the ramp of a new Fab in order to enhance the static capacity analysis. Their model demonstrated a method by which a full factory simulation was used to identify tools that might be regular limiters as a result of WIP flow, even if the static analysis showed there is suffi- cient capacity and did not elevate these tools as potential constraints throughout the ramp-up period of a new Fab. In this paper, we describe an extension of the above efforts, by demonstrating the utilization of a full factory simulation in order to analyze and support decisions that pertain to a transient period of parallel de-ramp and ramp- up of technologies in an existing Fab. Unlike the above references to typical simulation models for the analysis of factory performance and behavior in steady-state, or even the ramp of a new Fab, the transient model for parallel de- ramp and ramp-up’s of technologies in an existing Fab, poses several modeling challenges, which are discussed in this paper. The rest of the paper uses the following abbreviations: WSA (Wafers Starts Achievable), WIP (Work In Process), and WSPW (Wafer Starts Per Week). 2 PROBLEM STATEMENT During year 2005, Intel’s Fab-18 was facing a major chal- lenge of decreasing the volume of logic technology while ramping up volumes of chipset technology. The transition of moving from one technology to another occurred with very tight capacity due to high demand on the logic process that created some unexpected upsides in the required chip- set capacity. Towards the end of 2005, Fab-18 was faced with an additional challenge of starting-up a new flash technology. The need for aggressive start-up of the new technology has been driven by customer demands. The combination of increases in the required chipset capacity and the need for a fast ramp-up of flash, under the same clean-room space restrictions, resulted in a unique situation that the new flash technology had to be ramped with many A FULL FACTORY TRANSIENT SIMULATION MODEL FOR THE ANALYSIS OF EXPECTED PERFORMANCE IN A TRANSITION PERIOD Moti Klein Adar Kalir Intel Corporation Qiriat-Gat, ISRAEL 1836 1-4244-0501-7/06/$20.00 ©2006 IEEE