IEEE TRANSACTIONS ON COMPUTERS, VOL. c-27, NO. 12, DECEMBER 1978 A New Double-Rank Realization of Sequential Machines NICOLAOS GAITANIS AND CONSTANTINE HALATSIS Abstract-A new type of double-rank sequential circuit is pre- sented in this paper. This new type, called Type 4, differs from its predecessor types in that it employs a Boolean memory as rank-i memory instead of flip-flops. The Boolean memory used is an aggregate of symmetric Boolean memories with 1-out-of-n state encodings. A procedure for realizing a sequential machine by a Type 4 double-rank sequential circuit is also presented in the paper. Index Terms-Boolean memory, cyclic Boolean memory, double- rank circuits, excitation function, excitation matrix, flip-flop memory, n-flop, sequential machines, state assignment I. INTRODUCTION OUBLE RANK is a well-established technique for realizing sequential machines free of combinational hazards. Double-rank sequential circuits were originally introduced by Ware [1] in his attempt to design binary counters with simplified output logic. Systematic procedures for realizing sequential machines in double-rank mode have been presented by Hall [2], Unger [3], and Curtis [4]. The general block diagram of a double-rank sequential circuit may be thought of as in Fig. 1, where M1 is a collection of S-R flip-flops and M2 is a collection of either S-R [2], [3] or J-K [4] flip-flops. G 1 and G2 are, respectively, the excitation circuits of M1 and M2. C1 and C2 are two nonoverlapping synchronizing or clocking pulses of the first and second rank, respectively. The double-rank realization procedures developed thus far have led to three types of double-rank sequential circuits, namely Types 1, 2, and 3. Type 1 circuits are characterized by a minimum of rank-2 logic, G2, as shown in Fig. 2. The tandem of the S-R flip-flops of the first and the second rank actually form master-slave J-K flip-flops, so that methods used to derive state assignments for single-rank sequential circuits using J-K flip-flops can be applied also to Type 1 double-rank sequential circuits. Compared to Type 1, Type 2 double-rank sequential circuits have fewer flip-flops in the first-rank memory. The number of the first-rank states is equal to the least number of maximal compatibility classes which cover all the excitation patterns of the second-rank flip-flops [3]. Lastly, a Type 3 double-rank sequential circuit is similar to a Type 2 except that some or all the second-rank flip-flops are edge-triggered J-K flip-flops [4]. A Type 3 circuit has less logic circuitry than the corre- Manuscript received June 15, 1977; revised December 23, 1977 and May 17, 1978. 'The authors are with the Digital Systems Laboratory, Computer Center, Nuclear Research Center, Democritos, Aghia Paraskevi, Attikis, Athens, Greece. sponding Type 2, and a Type 2 less circuitry than the corresponding Type 1 [3], [4]. The new type of double-rank sequential circuit, called Type 4, differs from its predecessors in that the first-rank flip-flops have been replaced by a Boolean memory [5]. The Boolean memory considered is an aggregate of symmetric [5] Boolean memories with 1-out-of-n (or (n - l1out-of-n) state encodings called cyclic Boolean memories. A cyclic Boolean memory is a memory element having n equilibrium states (n = 2, 3, ) and it may be considered, for n > 2, a generalization of the S-R flip-flop. As such, a cyclic Boolean memory is excited in a straightforward manner [5]. As in the case of the Types 2 and 3 double-rank sequential circuits, the number of states which a Boolean memory assumes in a Type 4 circuit is equal to the number of the maximal compatibility classes of excitation patterns which cover all excitation patterns of the second-rank flip-flops. Furthermore, the state encoding of the Boolean memory is chosen in such a way that the rank-2 logic, G2, becomes a rail of AND gates as in the case of a Type 1 double-rank sequential circuit. This implies that -the outputs of the Boolean memory give directly the various excitation func- tions of the second-rank memory. Thus, the rank-I memory and the rank-2 logic of a double-rank sequential circuit are integrated into a Boolean memory. As it will be shown it is this integration that makes a Type 4 circuit in certain cases advantageous over its predecessors in terms of circuitry cost and speed of operation. In the following we present a procedure for realizing a machine M by a Type 4 double-rank sequential circuit. For illustration reasons rather than limitation of the method, a Type 2 procedure is assumed for deriving the state assign- ment and a minimal cover of the excitation patterns of the second-rank memory. Note, however, that the replacement of the first-rank flip-flops by a Boolean memory may be done either on a Type 2 or on a Type 3 circuit, that is, either a Type 2 or a Type 3 procedure may be used to derive the state assignment and the excitation patterns of the second-rank memory in a Type 4 circuit. For the sake of completeness the fundamental concepts on Boolean memories are revisted first in the next section. II. BOOLEAN MEMORIES According to Danielsson [5] a Boolean memory is an asynchronous sequential machine having the restricted flow table of Fig. 3 and may be realized by a digital net with 0018-9340/78/1200-1137$00.75 (© 1978 IEEE 1 137