TWO LOW-VOLTAGE HIGH-SPEED CMOS FREQUENCY-INSENSITIVE PWM SIGNAL GENERATORS BASED ON RELAXATION OSCILLATOR Montree Siripruchyanun*, Poolsak Koseeyaporn*, Jeerasuda Koseeyaporn**, Paramote Wardkein ** * Department of Teacher Training in Electrical Engineering, Faculty of Technical Education, King Mongkut’s Institute of Technology North Bangkok, Bangsue, Bangkok, 10800, THAILAND Email: mts@kmitnb.ac.th ** Department of Telecommunication Engineering, Faculty of Engineering, King Mongkut’s Institute of Technology Ladkrabang, Ladkrabang, Bangkok, 10520, THAILAND ABSTRACT In this paper, two new simple PWM (Pulse Width Modulation) signal generators based on modified CMOS relaxation oscillator are introduced. Translinear current dividers are proposed to improve the circuit performance such that it is frequency insensitive to the magnitude of an input signal. In addition, the precise PWM signal can be easily achieved under low voltage consumption and the output frequency can be ranged up to several megahertz. Furthermore, both voltage and current modulating signal can be applied. Based on the features and the simplicity of the circuits, it is very suitable for developing into Integrated Circuits (ICs) form in communication applications. The simulation results through PSPICE show a good agreement with theoretical anticipation. 1. INTRODUCTION A PWM signal is widely utilized in the areas of power electronics, instrumentation and communication systems, especially in optical communication. By the reason, the PWM signal generator has been realized in Integrated Circuits (ICs) form that makes it conveniently implemented. However, the circuit configuration is typically composed of current sources, flip-flop, comparators and analog switches as well [1]. It causes inevitably comprising of a bulk of transistors. Although, the recent literatures have proposed the simple PWM signal generators [2-3], the schemes have limitations in such maximum frequency of PWM output signal due to a slew rate of an active element and high supply voltage of operation. In addition, the duty cycle of PWM output signal does not linearly vary with modulating signal. They have subsequently some distortion after demodulation. Alternatively, a low- voltage high-speed PWM signal generations based on BJT relaxation oscillator has been introduced [4]. However, its PWM output frequency is dependent on squaring of an input signal frequency, causing a distortion in demodulation process. The purpose of this article is to present 2 new low-voltage PWM signal generators modified from the CMOS relaxation oscillator. The benefit of the proposed circuits is that they can yield the precise PWM output signal whose duty cycle is linearly dependent on a magnitude of the modulating (information) signal over a high-speed and low-voltage. In addition, by using CMOS translinear current divider, the PWM output frequency is insensitive to magnitude of an input signal and adjustable based on a bias current in the current divider section. In accordant of mathematical derivation, the circuit performances are also proved here through PSPICE simulations. 2. PRINCIPLE 2.1 The conventional CMOS relaxation oscillator The relaxation oscillators using source-coupled connection of CMOS are widely utilized in many areas, especially in communications [5] due to their abilities in high frequency performance. This causes them to be suitably developed into Voltage Controlled Oscillators (VCOs) and Current Controlled Oscillators (CCOs) forms [6-7]. Fig. 1 is a simplified diagram of a CMOS relaxation oscillator circuit demonstrating the presented principle. The circuit is derived from the source- coupled multivibrator configuration and can provide a square- wave output. Its operation can be briefly explained as follows. 1 M 2 M 3 M 4 M DD V I I C 1 R 2 R 1 S V 2 S V 1 D I 2 D I + C V + () o v t Fig. 1 The classical CMOS relaxation oscillator circuit 1 M and 2 M act as a gain stage. At any given time 1 M and 3 M or 2 M and 4 M are conducting, such that the capacitor C is alternately charged and discharged by constant current source I . The output across 3 M and 4 M corresponds to a symmetrical square wave, with a peak-to-peak amplitude of 2 GST V , where GST V is the MOS transistor threshold voltage. The output 1 S V is a constant when 1 M is on, and becomes a linear ramp with a slope equal to ( ) / I C when 1 M is off. The output () 2 S v t is the same as () 1 S v t , except for a half- cycle delay. Both of these linear ramp waveforms have peak- to-peak amplitudes of 2 GST V . The frequency of oscillation can be expressed as 4 O GST I f V C = (1) 2.2 The proposed principle The PWM signal output can be obtained by adjusting the charged and discharged constant current values to make them IV - 764 0-7803-8251-X/04/$17.00 ©2004 IEEE ISCAS 2004 ➠ ➡