Interface Engineering for InGaAs n-MOSFET Application
Using Plasma PH
3
–N
2
Passivation
Hoon-Jung Oh, Sumarlina Azzah Bte Suleiman, and Sungjoo Lee
*
,z
Department of Electrical and Computer Engineering, National University of Singapore, Singapore 119260
To realize high electron mobility metal-oxide-semiconductor field effect transistors MOSFETs on In
0.53
Ga
0.47
As with unpinned
Fermi level, a PH
3
–N
2
plasma treatment is proposed and preliminarily studied as a novel interface engineering technique, which
passivates the InGaAs surface by depositing a phosphorus nitride P
x
N
y
layer to suppress AsO
x
and free As. Comparative X-ray
photoelectron spectroscopy and atomic force microscopy studies reveal that a low pressure PH
3
–N
2
plasma treatment of
In
0.53
Ga
0.47
As results in a smooth and atomically thin 1 monolayer P
x
N
y
film as a main product, with a P-for-As anion
exchanged layer found beneath the P
x
N
y
layer in a practically wide range of process window. The process conditions affect the
stoichiometry of the P
x
N
y
layer, the amount of phosphorus and nitrogen atoms incorporated, and the degree of the P-for-As
exchange reaction. MOSFET devices integrated with metalorganic chemical vapor deposited HfO
2
/TaN metal gate on the passi-
vated In
0.53
Ga
0.47
As substrates have been fabricated by the conventional self-aligned gate-first process and compared to nonpas-
sivated MOSFETs. The excellent interface quality of P
x
N
y
passivated In
0.53
Ga
0.47
As /HfO
2
/TaN gate stack has been proven
showing suppressed frequency dispersion in inversion capacitance by 82–94% compared to the nonpassivated device and a low
subthreshold slope approaching the theoretical value of 60 mV/dec.
© 2010 The Electrochemical Society. DOI: 10.1149/1.3489946 All rights reserved.
Manuscript submitted December 21, 2009; revised manuscript received August 24, 2010. Published September 23, 2010.
Based on the high electron mobility and the direct bandgap prop-
erties of III-V compound semiconductor materials, III-V metal-
oxide-semiconductor field effect transistors MOSFETs have been
envisioned for high speed low power electronic devices with multi-
function over the past four decades. Recently, continued historical
scaling of Si-based metal-oxide-semiconductor MOS has been
threatened by its fundamental limits. Hence, approaches that include
changes in fundamental transistor structures, such as emerging
non-Si electronic materials onto the Si platform, are being explored,
as reviewed in the International Technology Roadmap for
Semiconductors.
1
In such development of microelectronic device
technology, III-V MOSFETs on GaAs, InGaAs, InSb, etc. are ac-
tively being studied by research groups in the industry as well as in
the academe.
2-7
However, the obstacle to realize III-V MOSFETs,
especially high performance enhancement mode E-mode MOS-
FETs, is the Fermi-level pinning issue, which is mainly due to the
poor interface qualities at the III-V/insulator interfaces
8-10
and also
the absence of a stable native oxide of III-V.
11
The recent successful demonstrations of E-mode III-V MOS-
FETs using advanced Si-based process techniques and in situ mo-
lecular beam epitaxy MBE,
2-4,6
as well as the achievement in un-
derstanding the Fermi-level pinning issue,
12
have shed light on the
future of emerging III-V nanoelectronics on Si platform. However,
the most difficult challenge to overcome is still on how to control
the interface qualities of III-V material systems in nanometer scale
devices such that detrimental effects due to high density surface
states and related Fermi-level pinning can be avoided. The common
features, which include subthreshold slopes SSs of over 150 mV/
dec and limited thermal budget found in the fabrication processes of
successful E-mode III-V MOSFETs,
2-7
may indicate this surface
state control issue on III-V surfaces. Moreover, as surface-to-volume
ratio is much increased in nanometer scale devices, this surface state
problem becomes more serious. Another important feature for future
III-V MOS devices is a high-k dielectric/metal gate stack.
1
Thus, the
success of future III-V nanoelectronics strongly depends on the
availability of a suitable and robust III-V surface passivation, which
can control surface states and related Fermi-level pinning, before
high-k deposition.
2,13
So far, the Si interface layer technique has been successfully
implemented to E-mode GaAs and InGaAs MOS devices, showing
the most promising device performance in scaled devices.
3,13
How-
ever the III-V/Si/high-k structure with the Si interface layer may
have significant inherent issues. Although the Si/high-k interfaces
have been well studied by present research groups with mature Si-
based process techniques, it still faces Fermi-level pinning issues as
well as low-k interfacial layer problem.
14
If the Si interface layer in
the III-V/Si/high-k stack is consumed by oxidation during device
fabrication processing, it would result in the low-k SiO
2
k = 3.9
interfacial layer and the III-V/SiO
2
interface to be inevitably pro-
duced. The interface of III-V/SiO
2
has been reported as one of the
sources of Fermi-level pinning.
12
In addition, the III-V/Si interface
should be examined with consideration of its thermodynamic stabil-
ity and the doping level of the channel, which can be perturbed by Si
diffusion into III-V.
15
Therefore, Si interface passivation with the
narrow process window may increase process complexity in device
fabrication to control the interfacial reaction. This is seen in the case
where the addition of nitridation treatment after deposition of the Si
interface layer
16
was to be carried out, and this may eventually limit
the scalability of III-V MOSFETs due to the two interfaces of III-
V/Si and Si/high-k.
As a novel approach to III-V surface passivation, we have re-
ported a phosphorus nitride P
x
N
y
layer as an interface passivation
layer for the InGaAs /HfO
2
/TaN metal gate stack structure, demon-
strating enhanced MOSFET performance and robust thermodynamic
stability of the gate stack integrity up to 800°C.
17,18
P
x
N
y
is a
chemically and thermodynamically stable material comprising group
V elements in the covalent bond,
19-21
and an E-mode InP MOSFET
using P
3
N
5
insulator as a gate dielectric was demonstrated with an
effective mobility of 1000–1640 cm
2
/V s in the early stage of III-V
MOSFET studies.
22
Because the most detrimental effects on the
III-V/oxide interface come from the volatile V oxide species,
9
espe-
cially from AsO
x
, passivating of the III-V surface in ultrahigh
vacuum with terminating group III element-rich III-V surface
13
or in
phosphorus- or nitrogen-rich ambient to switch to a more stable P-
or N-terminated III-V surface
23
is a good approach to achieve an
atomically abrupt and smooth interface that can inhibit the undesir-
able surface reactions of III-V materials for their MOS device ap-
plications. Similarly, the P
x
N
y
passivation process that we
reported
17,18
is based on plasma-assisted treatment by using 1%
PH
3
/N
2
mixture, which is one of the most common techniques and
reagents in the present Si platform integrated circuit industry. The
chamber atmosphere filled with PH
3
and N
2
and the stable product
of phosphorus nitride on III-V substrate may greatly suppress evo-
lutions of the undesirable oxides and group V vacancies in the pas-
sivation process before dielectric deposition because all the constitu-
ents are composed of group V elements. In addition, the presence of
hydrogen in the system can enhance the removal of V-group element
* Electrochemical Society Active Member.
z
E-mail: elelsj@nus.edu.sg
Journal of The Electrochemical Society, 157 11 H1051-H1060 2010
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