IOSR Journal of Electronics and Communication Engineering (IOSR-JECE) e-ISSN: 2278-2834,p- ISSN: 2278-8735. Volume 7, Issue 1 (Jul. - Aug. 2013), PP 05-11 www.iosrjournals.org www.iosrjournals.org 5 | Page Hardware Implementation of OFDM system to reduce PAPR using Selective Level Mapping on FPGA Rajesh S. Bansode 1 , Dr. B. K. Mishra 2 and Aqsa M. Temrikar 3 1 (I.T Department, Thakur College of Engineering and Technology, India) 2 (Principal, Thakur College of Engineering and Technology, India) 3 (M.E student, Thakur College of Engineering and Technology, India) Abstract : OFDM is a modulation as well as multiplexing technique which is widely used in various high speed mobile and wireless communication systems because of its capacity of ensuring high level robustness against interference. In this paper the design and implementation of OFDM system along with SLM implementation to reduce PAPR[6]is illustrated and a detailed simulation of the OFDM system with 16-QAM. OFDM transceiver is implemented using FPGA Spartan6 kit. The hardware results show a detailed study of RTL schematics and Test Bench. In this paper, the software simulation results show 2dB reduction in the peaks. Keywords - Field Programmable Gate Array, Matlab Simulink, Orthogonal Frequency Division Multiplexing , Peak-to-Average Power Ratio, Selective level Mapping and Xilinx I. INTRODUCTION Orthogonal Frequency Division Multiplexing (OFDM) is an attractive multicarrier technique for mitigating the effects of multipath delay spread of radio channel, and hence accepted for several wireless standards as well as number of mobile multimedia applications. Alongside its advantages such as robustness against multipath fading, spectral efficiency and simple receiver design, OFDM has two major limitations. One of these is its sensitivity to carrier frequency offsets (CFO) caused by frequency differences between the local oscillators in the transmitter and the receiver , phase noise and the other is high peak to average power ratio (PAPR) . This high PAPR is due to the summation of sinc-pulses and non-constant envelope. Therefore, RF power amplifiers (PA) have to be operated in a very large linear region. Otherwise, the signal peaks get distorted, leading to intermodulation distortion (IMD) among the subcarriers and out-of-band radiation. A simple way to avoid is to use PA of large dynamic range but this makes the transmitter. The paper aims at successful implementation of the transceiver on a FPGA which would pave a way towards developing an OFDM system which resolves the issue of high PAPR. Simulation results using System Generator and Matlab/Simulink and XILINX tools have been given.Finally it aims at development of a complete system which then results in robust, maximum throughput, highly scalable wireless LAN network. II. OFDM , PAPR AND SLM 2.1 General OFDM Block Diagram Descriptions 2.1.1 OFDM Transmitter The model considered for the implementation of the OFDM transmitter is the shown below and basically consist of [13] Serial to parallel converter, Constellation modulator, IFFT block, Parallel to serial converter, Digital to Analog converter, Selective Level Mapping 2.1.2 OFDM Receiver OFDM receiver is the shown below and basically consist of [13] Analog to digital converter, Serial to parallel converter, Cyclic prefix removal, FFT block, M-QAM decoder, Parallel to serial converter.