Improved retention for a Al 2 O 3 IPD embedded Flash cell without top-oxide J. R. Power , D. Shum, Y. Gong, S. Bogacz, J. Haeupel, H. Estel, R. Strenz Infineon Technologies Dresden, GmbH & Co. OHG Dresden, Germany john.power@infineon.com R. Kakoschke, K van der Zanden*, R. Allinger Infineon Technologies AG Munich, Germany *Infineon assignee at IMEC, Belgium ronald.kakoschke@infineon.com G. Jaschke Qimonda Dresden, GmbH & Co. OHG Dresden, Germany Abstract— Using a 2Mb embedded Flash cell array as a demonstrator, we reported previously that a 3V reduction in programming voltage was possible by replacing the ONO inter- poly dielectric (IPD) with an IPD comprising the high-k material, Al 2 O 3 [1]. Adding a thin protective top-oxide to the high-k IPD was later shown to significantly improve reliability [2]. In this paper, we show that for integration schemes more suited to the material properties of Al 2 O 3 , reliably functioning 2Mb demonstrators with a high-k IPD but without top-oxide protection are also feasible. I. INTRODUCTION Through the higher coupling of control-gate (CG) voltage to floating gate (FG) afforded by high-k materials over conventional ONO as an IPD, the required programming voltage may be reduced. This enables a shrink of all peripheral high-voltage (HV) circuitry, leading to an overall reduction in chip size and thus chip cost. Here, Al 2 O 3 is a good candidate, being a well known high- k material that has already reached the required level of maturity [3-5]. Successful integration and data retention have already been demonstrated on single-cells [4] and small 26kbit arrays [5], and more recently by us on 2Mb arrays [1,2]. In reference 1, we reported data for several high-k IPD constructions with different bottom oxide and Al 2 O 3 thicknesses and indicated that 4nm of bottom oxide was required to obtain sufficient retention. However, only room temperature retention data was presented and several integration issues hindered general conclusions to be made concerning IPD layer construction and reliability. In reference 2, we showed that promising retention could be achieved even at higher temperature by adding a top-oxide to the IPD construction. However, tail-bits were observed indicating integration problems still remained. In this paper we extend our work on 2Mb arrays and report, through several process improvements, the successful integration of Al 2 O 3 as an IPD material for two different integration schemes, both with bottom-oxide but without top- oxide. Also, we show that acceptable reliability may be obtained for a high-k IPD even without bottom-oxide. Finally, we compare these results with those previously reported for the high-k IPD construction with top-oxide [2]. The 2Mb arrays, comprising of 1-T UCP flash cells, were processed in an established 130nm node eFlash technology, where the conventional ONO IPD was replaced with the high- k IPD comprising Al 2 O 3 . The Al 2 O 3 was deposited by atomic layer deposition (ALD) using trimethylaluminium (TMA) and ozone precursors. A post deposition anneal (PDA) of 1000°C for a duration of 60s was used to crystallize the deposited amorphous Al 2 O 3 layer. The high-k IPD comprised either a bottom oxide (4nm) and Al 2 O 3 (10nm) layer, or an Al 2 O 3 only layer (15nm). As time coupling was unavailable before Al 2 O 3 deposition, a native bottom-oxide of 1nm could not be ruled out for 15nm Al 2 O 3 split-group. Hence, in the following, we refer to these IPD constructions as 4/10 or 1/15. Two different integration schemes were employed (see Fig.1). In scheme A, the Al 2 O 3 layer was exposed to several wet chemical processing steps High-k IPD deposition/anneal Gate oxide growth CG poly deposition Scheme B Scheme A Logic well definition Well impl. / resist strips Gate oxide pre-cleans High-k IPD deposition/anneal Gate oxide growth CG poly deposition Scheme B Scheme A Logic well definition Well impl. / resist strips Gate oxide pre-cleans Figure 1 : Schematic of process flow for scheme A and scheme B directly after high-k deposition. In scheme B, the 2 nd CG poly is removed (not shown) before gate structuring. High-k IPD deposition/PDA Gate oxide growth CG poly deposition Scheme B Scheme A Logic well definition Well impl. / resist strips Gate oxide pre-cleans High-k IPD deposition/PDA Gate oxide growth CG poly deposition Scheme B Scheme A Logic well definition Well impl. / resist strips Gate oxide pre-cleans Figure 1 : Schematic of process flow for scheme A and scheme B directly after high-k deposition. In scheme B, the 2 nd CG poly is removed (not shown) before gate structuring. 93 978-1-4244-1547-2/08/$25.00 (c)2008 IEEE