Automated Synthesis of Delay-Reduced Reed-Muller Universal Logic Module Networks Shahana T. K, Rekha K. James, K. Poulose Jacob Cochin University of Science and Technology Kochi, Kerala, India E-mail:{shahanatk, rekhajames, Abstract This paper presents a new approach to implement Reed-Muller Universal Logic Module (RM-ULM) networks with reduced delay and hardware for synthesizing logic functions given in Reed-Muller (RM) form. Replication of single control line RM-ULM is used as the only design unit for defining any logic function. An algorithm is proposed that does exhaustive branching to reduce the number of levels and modules required to implement any logic function in RM form. This approach attains a reduction in delay, and power over other implementations of functions having large number of variables. 1. Introduction Every Boolean function can be expressed in terms of Reed-Muller (RM) expansion. This representation has various advantages such as ease of complementing and testing, and reduction in number of product terms leading to smaller circuits on-chip over the conventional descriptions [1]. Several papers have been published discussing design and minimization techniques for RM logic, derivation of various polarities, as well as conversion between RM and Boolean forms [4, 7, 8]. RM functions can be implemented using discrete components or more conveniently by RM-ULMs. An RM-ULM is a device with c-control inputs, 2c data inputs and a single output f(c) and is designated as RM- ULM(c). The behavior of this module is described as f(c) = bo ®) blxl ® b2x2 ® b3x2x1 ) .... ® b2C 1xcXc ....XI 2c -1 =®@biPi i=O where bi = 0 or 1, and the product term (or piterm) Pi is, P =x x. ....x I ic Ic - 1 11 c-l where i = E 2i xj j=o x will be present in Pi if the kth bit of binary representation for i is 1. The logic symbol for RM-ULM(c) is shown in Figure 1. Sreela Sasi Gannon University Erie, PA, USA sasiOO1 gannon.edu b C xc XI Figure 1. Logic symbol of RM-ULM(c) VLSI implementations using only one type of modular building blocks can decrease system design and manufacturing cost. For functions in RM form speed and cost can be reduced by using RM-ULMs connected in tree structure. A tree network is very suitable for VLSI realization because of the uniform interconnection structure and the repeated use of identical modules. The use of RM-ULM for realization of logic functions has already been explored by researchers. A programmed algorithm was developed by L. Xu [2], which is analogous to the algorithm in [6], for optimization of number of modules at sub-system level in a tree network. The algorithm looks for possible cascade networks, and if it is not found a tree structure is implemented. An alternate algorithm was presented by E. C. Tan [3], which performs similar optimization of fixed polarity general Reed-Muller expansions (FPGRM) with a reduced computation time. The above algorithms do not explore all the possible branching options of the tree structure and hence the delay of the circuit synthesized may not be minimal. In this research, further delay reduction is achieved by using a novel tree-structured exhaustive branching network using RM-ULM(1) for implementing a logic function given in positive polarity Reed-Muller (PPRM) form. A logic function with n-variables can be implemented using 2_-1 RM-ULM(I)s in n - levels by standard implementation. Any implementation using less than 2-_1 number of modules and / or lesser number of levels can be considered as an improvement in cost and or speed. The organization of this paper is as follows: First, the problem is described and then the proposed exhaustive branching algorithm is demonstrated with examples. Finally, a comparison in terms of delay and number of modules is done for standard implementation and tree implementation [2, 3] for several functions.