International Journal of Computer Applications (0975 8887) Volume 59 - No. 11, December 2012 A Low Power 90nm Technology based CMOS Digital Gates with Dual Threshold Transistor Stacking Technique P. S. Aswale M.E. VLSI & Embedded Systems Department of ETC Engineering SITRC, Nashik, Maharashtra, India S. S. Chopade Associate Professor Department of ETC Engineering SITRC, Nashik, Maharashtra, India ABSTRACT Scaling of transistor features sizes has improves performance, in- crease transistor density and reduces the power consumption. A chip’s maximum power consumption depends on its technology as well as its implementation. As technology scales down and CMOS circuits are powered by lower supply voltages, leakage current becomes significant. static power is becoming the pre- dominant source of energy waste. To create methodologies that support efficient designs, good performance, lower costs in the era of low power, is up to the design, EDA community . As the threshold voltage is reduced due to scaling, it leads to in- crease in sub threshold leakage current and hence increase in static power dissipation. This paper presents performance analy- sis of inverter using conventional CMOS, stack and dual thresh- old transistor stacking techniques. The performance analysis of inverter were analyzed in 90nm technology using Cadence vir- tuoso environment. The use of dual threshold voltages can sig- nificantly reduce static power dissipated in CMOS VLSI circuits. General Terms: Low Power Design Keywords: CMOS inverter, static power, threshold voltage, transistor stacking, ULSI. 1. INTRODUCTION In early 1970’s, providing high speed operation with minimum area were main aim of design. Many design tools are concentrated to achieve these goals. ITRS reported that leakage power consumption may come to dominate total chip power consumption as technology feature size shrinks [7,8]. As we can observed that static consump- tion tends to increase over the year as dynamic power consumption [8]. The increasing prominence of portable systems and the need to limit power consumption in very high density ULSI chips have lead to rapid and innovative development in low power design. Due to power sensitive portable devices, low power is very important requirement of all high performance application where power is one of the important design constraints. In today’s era of VLSI, Fig. 1. Power consumption prediction by the ITRS 2009[8]. power consumption control and management has become a key challenge and critical issue in electronics industry. The advance- ment in VLSI technology allows integrating a complete system on chip (SoC) providing facility to develop a portable system. Power dissipation is a critical parameter in battery operated portable de- vice. The limited battery Lifetime typically imposed very strict de- mands on the overall power consumption of the portable systems. Power consumption is one of the important factors of VLSI circuit design for CMOS is the primary technology. The power consump- tion has become a fundamental problem in VLSI circuit design. Therefore, reducing the power consumption of integrated circuits through design improvement is a major challenge in portable sys- tem design. To solve the power consumption problem, many dif- ferent techniques from circuit level to device level and above have been proposed by researchers. However, there is no straight for- ward ways to meet the tradeoff between power, delay and area. The designers are required to choose appropriate techniques that satisfy the application and product needs [2]. Reducing power dis- sipation varies from application to application. The key objective in reducing power consumption is to reduce the overall cost of the product. One of the most challenging problem is to find out new and effective circuit design technique to reduce the overall power dissipation without compromising the performance of the device. Scaling advanced CMOS technology improves high performance and high transistor density. The power dissipation of a chip depend 47