546 IEEE TRANSACTIONS ON ELECTRON DEVICES, VOL. 46, NO. 3, MARCH 1999 Recent Progress of Submicron CMOS Using 6H–SiC for Smart Power Applications Man Pio Lam and Kevin T. Kornegay, Senior Member, IEEE Abstract— Silicon carbide (SiC) CMOS circuits have been developed recently to provide monolithic control for SiC MOS power switching devices. Although SiC CMOS is not well suited for high-end microprocessor applications, it must provide the necessary response time performance required for safe operation in high-voltage power switching applications. Despite previous developments in SiC CMOS process technology, which have enabled digital circuit operation using a 5 V power supply, circuit switching speeds were in the microsecond range. An obvious way to improve circuit performance is to scale device lateral and vertical dimensions. This paper describes recent progress in the development of a submicron, single metal, p-well CMOS process technology using 6H-SiC. Conventional NMOS transistors are fabricated with 0.5-mm (drawn) channel lengths and exhibit acceptable short-channel effects. Conventional PMOS transistors exhibit punchthrough at 0.8-mm channel lengths and require considerable channel engineering efforts which are also presented. Several digital logic gates and a ring oscillator have been fabricated with nanosecond gate switching performance. Performance limiting factors like parasitic series resistance is also investigated. Index Terms—High-temperature, MOSFET’s, silicon carbide. I. INTRODUCTION T HE advantage of complementary technologies is the availability of current source loads which provide large voltage gains with relatively small supply voltages and cur- rents. Advances in SiC process technology have led to the development of CMOS circuits. The first complementary de- vice technology using 6H-SiC enhancement-mode MOSFET’s demonstrated a functional operational amplifier with a DC gain of about 10 (80 db) [1]. However, the threshold voltage for the p-channel devices fabricated in an implanted n-well was around 17 V. The high threshold voltage requires a large power supply voltage which is incompatible with the conventional CMOS digital logic. Recently, an implanted p-well CMOS process has been successfully developed to fabricate digital circuits using a lower supply voltage [2]. The threshold voltage for the NMOS and PMOS devices were 3 and 8 V, respectively. In [3], the authors demonstrate SiC CMOS logic circuits operating on a 5 V power supply. The lower supply voltage reduces the stress on the thermal oxide, Manuscript received October 10, 1998. This work was supported by ONR under Contracts N00014-96-10562 and N00014-98-10495. The review of this paper was arranged by Editor K. Hara. M. P. Lam is with Motorola, Tempe, AZ 85285 USA. K. T. Kornegay is with the School of Electrical Engineering, Cornell University, Ithaca, NY 14853-5401 USA. Publisher Item Identifier S 0018-9383(99)01683-4. and thus provides the greatest opportunity for reliable circuit operation. CMOS and most power MOS transistors (DIMOS and lateral DMOSFET [4], [5]) in SiC were developed using boron implantation to form a p-well in an n-type SiC epilayer. The compatibility of their processes eases integration of the power device and CMOS digital control circuits on the same SiC wafer to from a smart power IC. Because SiC power switching devices operate at high-current and high-power levels, self- heating is expected to cause device junction temperatures to exceed 350 C. Therefore, the circuits implmenting the support electronics on a smart power chip must provide reliable and stable operation over a wide range of temperatures. Because of its wide bandgap, SiC NMOS and CMOS circuits have demonstrated stable operation ranging from room temperature to 300 C [3], [6]. Smart power technology usually combines detection cir- cuitry together with digital and analog feedback control to protect the IC from catastrophic failure. CMOS operational amplifiers and intelligent gate drivers that provide stable op- eration at elevated temperatures have already been performed on SiC [7], [8]. As a robust smart power system becomes more complex, CMOS circuits are required to have higher performance and higher density in order to provide the control, diagnostic, and self-protection functions. The response time of these circuits is critical to a benign shutdown because the power load current will increase very abruptly during an over-current or over-voltage fault. For medium-frequency applications such as adjustable speed motor drives, turn-off times of power device range from 0.1 to 10 s [9]. The turn- off time of SiC power switching device in the range of 0.1 s has already been demonstrated in [10]. As the high-speed operation of power devices is required, the protection of the system can only be accomplished by utilizing suitably fast control circuits to provide the necessary response. However, current CMOS digital logic circuits can only operate with a gate delay per stage of 442 s with a VDD of 5 V, and 0.45 s for a VDD of 20 V. With this technology, even a single inverter stage is incapable of turning off a power system in a rapid response time. Scaling of device dimensions is the main force of increasing circuit speeds. This critical issue has led to the development of a submicron CMOS technology in 6H-SiC capable of providing the performance suited for smart power applications. In this paper, a submicron CMOS technology with sub- 0.1- s gate delays was developed aiming at the smart power application. For this study, CMOS devices in 6H-SiC are 0018–9383/99$10.00  1999 IEEE