Coplanar Integration of Lattice-Mismatched Semiconductors with Silicon by Wafer Bonding GeÕ Si 1 Àx Ge x Õ Si Virtual Substrates Arthur J. Pitera, z G. Taraschi, M. L. Lee, C. W. Leitz,* Z.-Y. Cheng, and E. A. Fitzgerald Department of Materials Science and Engineering, Massachusetts Institute of Technology, Cambridge, Massachusetts 02139, USA We have demonstrated a general process which could be used for the integration of lattice-mismatched semiconductors onto large, Si-sized wafers by wafer bonding Ge/Si 12x Ge x /Si virtual substrates. The challenges for implementing this procedure for large diameter Ge-on-insulator ~GOI! have been identified and solved, resulting in the transfer of epitaxial Ge/SiO 2 to a Si wafer. We found that planarization of Ge virtual substrates was a key limiting factor in the transfer process. To circumvent this problem, an oxide layer was first deposited on the Ge film before planarization using a standard oxide chemical mechanical planarization process. The GOI structure was created using H 2 -induced layer exfoliation ~Smartcut™! and a buried Si 0.4 Ge 0.6 etch-stop layer, which was used to subsequently remove the surface damage with a hydrogen peroxide selective etch. After selective etching, the crosshatched surface morphology of the original virtual substrate was preserved with roughness of ,15 nm rms as measured on a 25 3 25 mm scale and a 1 3 1 mm scale roughness of ,1.4 nm. Using an etch-stop layer, the transferred device layer thickness is defined epitaxially allowing for future fabrication of ultrathin GOI as well as III-V films directly on large-diameter Si wafers. © 2004 The Electrochemical Society. @DOI: 10.1149/1.1757462# All rights reserved. Manuscript submitted July 14, 2003; revised manuscript received January 16, 2004. Available electronically May 19, 2004. The overwhelming success of silicon in modern microelectronics can be attributed to its high-quality native oxide. This eventually led to complementary metal oxide semiconductor ~CMOS! circuit topol- ogy, dense digital integrated circuits ~ICs!, and large diameter wa- fers and manufacturing infrastructure. Advances in IC performance are currently achieved through dimensional scaling of device geom- etries. However, this trend cannot continue indefinitely since device features will soon approach atomic dimensions. Fundamental mate- rial properties of silicon including its low carrier mobility and indi- rect bandgap are becoming limiting factors in further improvement of integrated circuit functionality and performance. CMOS functionality can be vastly improved through monolithic integration of high-performance materials such as Ge and III-V semiconductors with Si. The monolithic approach allows these ma- terials to be co-processed on the same substrate, eliminating expen- sive back-end hybrid integration of independently processed Si and III-V devices. Such a method can be realized using Si, Ge, or III-V substrates. However, in order to take advantage of state-of-the-art CMOS fabrication facilities and preserve the economics of fabrica- tion on large diameter substrates, it is necessary to integrate these materials on the Si platform. The ;4% lattice mismatch between Si and GaAs or Ge pre- cludes direct growth of the mismatched material on Si without nucleation of a high ( .10 8 cm 22 ) density of threading dislocations. 1 These defects behave as carrier recombination centers and have a deleterious effect on performance, particularly for minor- ity carrier devices. Although optoelectronic devices, including la- sers, have been demonstrated on GaAs grown directly on Si, 2-5 their poor reliability makes them commercially unfeasible. One technique to reduce the threading dislocation density ~TDD! is the growth of compositionally graded buffers. 6 During graded buffer growth, a large lattice constant mismatch is diluted over many low-mismatch interfaces thereby controlling the nucleation rate of threading dislo- cations. Compositional grading of relaxed Si 12x Ge x layers of in- creasing Ge fraction can be used to create an arbitrary lattice con- stant ranging from that of Si to Ge on a bulk Si substrate. Such a structure is termed a virtual substrate. Ge virtual substrates can be used to integrate III-V materials with Si 7 since the lattice mismatch between Ge and GaAs is only 0.07%. These have enabled fabrica- tion of compound semiconductor lasers 8,9 and an optical circuit 10 utilizing an LED emitter, waveguide, and detector monolithically integrated on a Si wafer. Despite its ability to produce lattice- mismatched epitaxy of unprecedented quality, the virtual substrate approach requires growth of a thick graded buffer to ensure com- plete relaxation of the individual mismatched layers. In the case of Ge virtual substrates which are compositionally graded from Si to Ge, the buffer thickness is typically greater than 10 mm. Such thick layers complicate subsequent device integration with the underlying Si since the device levels are not coplanar and must be co-processed across a deep step. Wafer bonding and layer transfer 11,12 is another approach that can be used to integrate low-defect, lattice mismatched materials with Si. In the direct bonding method, a Si handle wafer and a mismatched seed wafer are brought into contact and annealed to produce a strong bond. A thin, monocrystalline layer of material is then transferred from the seed to the handle wafer by a variety of techniques including grind and etch-back 13 or layer exfoliation by hydrogen ion implantation, i.e., Smartcut. 14 However, conventional wafer bonding using bulk wafers has two serious limitations. First, the different coefficients of thermal expansion ~CTE! of Si (2.57 3 10 26 K 21 ) 15 relative to GaAs (6.03 3 10 26 K 21 ) 16 and Ge (5.90 3 10 26 K 21 ) 15 require a low thermal budget during bond an- nealing. Thermal stress 17 arising from CTE mismatch will cause the bonded pair to separate after annealing at high temperature. 18 The thermal stress problem between thermally mismatched wafers can be handled using the Smartcut approach where a thin layer of ma- terial is transferred from bulk GaAs 19 or Ge 20 to Si prior to cooling the bonded pair to ambient. A more serious issue is the wafer size difference between Si and III-V or Ge wafers. Films transferred to Si from III-V-sized wafers limit their use to outdated fabrication facili- ties running small diameter Si wafers for low-end CMOS applica- tions. Although a limited supply of Ge bulk wafers are available in large diameters, their current production volume is too small to sus- tain the CMOS industry. The advantages of virtual substrates and layer transfer using wa- fer bonding can be combined by bonding virtual substrates rather than bulk wafers. By transferring epitaxially grown layers from vir- tual substrates, Ge or III-V films can be fabricated in close proxim- ity to a Si substrate while taking advantage of the full diameter of modern Si wafers. This approach also eliminates the thermal stress that arises during bulk wafer-bonding since both seed and handle wafers are bulk Si. * Electrochemical Society Active Member. z E-mail: pitera@mit.edu Journal of The Electrochemical Society, 151 ~7! G443-G447 ~2004! 0013-4651/2004/151~7!/G443/5/$7.00 © The Electrochemical Society, Inc. G443