Level-Shifter Free Design of Low Power Dual Supply Voltage CMOS Circuits Using Dual Threshold Voltages Abstract Usage of dual supply voltages in a digital circuit is an effective way of reducing power consumption due to the quadratic relation of supply voltage to power consumption. But the need for level shifters when a low voltage gate drives a high voltage gate has been a limiting factor preventing widespread usage of dual supply voltages in digital circuit design. The overhead of level shifters forces designers to increase the granularity of dual voltage assignment, reducing the maximum obtainable savings. We propose a method of applying dual supply voltages at gate level granularity without using level shifters. We modify the threshold voltage of the high voltage gates that are driven by low voltage gates in order to obtain the level shifting operation together with the logic operation. Using our method, we obtained an average of 20% energy savings for ISCAS’85 benchmark circuits. 1. Introduction Energy consumption in CMOS circuits is proportional to the square of the supply voltage. This makes dual supply voltage usage popular for energy reduction. Since the speed of a gate decreases with decreasing supply voltage, dual supply voltage techniques [1][2][3][5][6][7][8] put low-voltage gates on the non- critical paths and high-voltage gates on the critical paths. This reduces the energy consumption in the low voltage gates while keeping the circuit delay unchanged. Gate level dual supply voltage usage in CMOS circuits may suffer from excessive leakage energy if low voltage gates directly drive high voltage gates. In these situations, the PMOS transistor in the high voltage gate is not turned off completely with the low voltage “logic high” input signal. This leads to the use of level shifters wherever low voltage gates drive high voltage gates. To reduce or eliminate the delay, area, and energy overhead of the level shifters, researchers have proposed Clustered Voltage Scaling (CVS) [5][6] and Module Level Voltage Scaling (MLVS) [7][8]. In CVS, low voltage clusters are constructed in the circuit in such a way that there is no low voltage gate driving a high voltage gate. This is done by assigning low supply voltage to the gates starting from the circuit outputs depending on their slacks. Even though this method eliminates the use of level shifters, it cannot exploit the maximum energy savings possible with dual supply voltages. MLVS assigns the dual supply voltages to partitions of the circuit. This reduces the number of level shifters needed. Clearly this method also can not exploit the maximum energy savings possible with dual supply voltage usage since slacks of the gates in high voltage modules are not exploited. There has also been research in the usage of gate level dual supply voltages with level shifters being used whenever a low voltage gate drives a high voltage gate [1][2][3]. In [1] and [2], graph theoretic algorithms are employed to apply dual supply voltage at the gate level while keeping the delay constant. [3] is an extension to CVS where level shifters are not restricted to be only in sequential elements. These algorithms try to minimize the number of level shifters used in the circuit to reduce their area, energy and delay overhead. However, apart from the area, energy and delay overhead, level shifters also decrease the slacks of the other gates in the same path, thereby reducing the number of gates that can operate with a lower supply voltage. In this paper, we propose a circuit technique to eliminate the need for additional level shifter use in dual supply CMOS circuit design. We use a second threshold voltage in the PMOS transistors of the high voltage gates driven by low voltage gates, thereby providing them with built-in level-shifting capability. These modified gates have no energy or area penalties and only a slight delay penalty over the regular high voltage gates. The delay overhead is much less than a conventional level shifter delay, which is usually close to two inverter delays [4]. A similar approach for level shifter implementation is used in [4] where logic functionality is embedded into level Abdulkadir U. Diril, Yuvraj S. Dhillon, and Abhijit Chatterjee Georgia Institute of Technology, Atlanta, GA { utku,yuvrajsd,chat}@ece.gatech.edu Adit D. Singh Auburn University, Auburn, AL adsingh@eng.auburn.edu This work was supported by NSF Information Technology Research Contract, CCR 022-0259