IEEE TRANSACTIONS ON COMMUNICATIONS, VOL. 56, NO. 7, JULY 2008 1025 Transactions Letters Sequential Message-Passing Decoding of LDPC Codes by Partitioning Check Nodes Sunghwan Kim, Min-Ho Jang, Jong-Seon No, Member, IEEE, Song-Nam Hong, and Dong-Joon Shin, Member, IEEE Abstract—In this paper, we analyze the sequential message- passing decoding algorithm of low-density parity-check (LDPC) codes by partitioning check nodes. This decoding algorithm shows better bit error rate (BER) performance than the con- ventional message-passing decoding algorithm, especially for the small number of iterations. Analytical results indicate that as the number of partitioned subsets of check nodes increases, the BER performance is improved. We also derive the recursive equations for mean values of messages at check and variable nodes by using density evolution with a Gaussian approximation. From these equations, the mean values are obtained at each iteration of the sequential decoding algorithm and the corresponding BER values are calculated. They show that the sequential decoding algorithm converges faster than the conventional one. Finally, the analytical results are confirmed by the simulation results. Index Terms—Density evolution, flooding schedule, low-density parity-check (LDPC) codes, message-passing decoding, sequential decoding. I. I NTRODUCTION I N 1996, low-density parity-check (LDPC) codes, originally invented by Gallager [1], were rediscovered by MacKay and Neal [2]. Since then, LDPC codes have been the main research topic in the coding area because they show the capacity-approaching performance with feasible complexity [3], [4]. Compared with turbo codes, they have lower decoding complexity due to the message-passing decoding based on the sum-product algorithm [5], but slower decoding convergence speed. An LDPC code can be defined by a very sparse parity-check matrix which contains mostly 0’s and a few 1’s. The sparseness of the parity-check matrix gives low decoding complexity and better decoding performance. LDPC codes can be classified into two classes according to the degrees of variable nodes and check nodes. If the degrees of variable nodes and check nodes of an LDPC code are d v and d c , respectively, it is called a Paper approved by A. H. Banihashemi, the Editor for Coding and Commu- nication Theory of the IEEE Communications Society. Manuscript received September 24, 2004; revised June 30, 2005, February 26, 2006, and March 8, 2007. This work was supported by the MOE, the MOCIE, and the MOLAB, Korea, through the fostering project of the Laboratory of Excellency. This paper was presented in part at ISITA, Seoul, Korea, October 2006. S. Kim, M.-H. Jang, and J.-S. No are with the Department of Electrical Engineering and Computer Science, Seoul National University, Seoul 151- 742, Korea (e-mail: {nodoubt, mhjang}@ccl.snu.ac.kr; jsno@snu.ac.kr). S. Hong and D.-J. Shin are with the Department of Electronics and Computer Engineering, Hanyang University, Seoul 133-791, Korea (e-mail: sunny795@ccrl.hanyang.ac.kr; djshin@hanyang.ac.kr). Digital Object Identifier 10.1109/TCOMM.2008.040571. (d v ,d c ) regular LDPC code. Otherwise, it is called an irregular LDPC code. Recently, there have been a lot of efforts on implementing LDPC decoder efficiently. In general, hardware implementa- tion of LDPC decoder uses parallel processing. However, if the decoder cannot be implemented in the fully parallel processing mode, sequential decoding approach has to be taken. An efficient sequential decoding algorithm and its hard- ware implementation are introduced in [6], where messages between each variable node and its neighbors are sequentially updated. A novel shuffled iterative decoding by partitioning variable nodes is introduced in [7]. This scheme has the same computational complexity as the iterative decoding based on flooding schedule and by simulation it is shown to converge faster. Similarly, a message-passing decoding algorithm which is sequentially performed on each variable node is introduced in [8] and the fast convergence of this algorithm is also verified by simulation. In [9]–[11], turbo product codes/single- parity check (TPC/SPC) codes are investigated, in which the message-passing decoding is performed by partitioning check nodes into two groups. Note that, in this paper, the sequential message-passing decoding algorithm based on various check node partitioning schemes is analyzed. In [12] and [13], various new schedules have been pro- posed, in which the messages are exchanged at each iteration according to the parameters of the Tanner graph [14] such as the girths and the closed walks of the nodes. They are categorized as node based versus edge based, unidirectional versus bidirectional, and deterministic versus probabilistic, and the performance/complexity tradeoff is studied through simulation. Reliability-based schedule is also proposed, which performs the message-passing decoding using the reliability of each bit node instead of graph parameters [15]. In [16] and [17], new serial LDPC decoding algorithms which can be considered as the decoding using check node partitioning are introduced. They are especially suitable for hardware imple- mentation. Also, by simulation, they are shown to converge faster than the iterative decoding based on flooding schedule. In the conventional fully parallel message-passing decod- ing algorithm, many iterations (50 or more) are required to achieve the desired performance, which results in high decoding complexity. To reduce the number of iterations (or decoding complexity), the decoding should converge faster. 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