The Instruction-Set Extension Problem: A Survey Carlo Galuzzi and Koen Bertels  Computer Engineering, EEMCS Delft University of Technology, The Netherlands {C.Galuzzi,K.L.M.Bertels}@ewi.tudelft.nl Abstract. Over the last years, we have witnessed the increased use of Application-Specific Instruction-Set Processors (ASIPs). These ASIPs are processors that have a customizable instruction-set, which can be tuned towards specific requirements. The identification, definition and implementation of those operations that provide the largest performance improvement and that should be hardwired, extending in this way the Instruction-Set, constitutes a major challenge. The purpose of this paper is to investigate and study the issues regarding the customization of an Instruction-Set in function of the specific requirements of an application. Additionally, the paper provides an overview of all relevant aspects of the problem and compensates the lack of a general view of the problem in the existing literature. 1 Motivation Electronic devices are very common in everyday life. It’s enough to think about mobile phones, digital cameras, etc. This great variety of devices can be im- plemented using different approaches and technologies. Usually these function- alities are implemented using either General Purpose Processors (GPPs), or Application-Specific Integrated Circuits (ASICs), or Application-Specific Instruc- tion-Set Processors (ASIPs). GPPs can be used in many different applications in contrast to ASICs which are processors designed for a specific application such as the processor in a TV set top box. The main difference between GPPs and ASICs is in terms of flexibility. The programmability of GPPs supports a broad range of possible applications but usually leads to more power consumption due to the inefficient units consump- tion. On the other hand, ASICs are able to satisfy specific constraints such as size, performance and power consumption using an optimal architecture for the application, but today designing and manufacturing an ASIC is a long and ex- pensive process [1]. This design complexity grows exponentially due to shrinking geometries and the high mask and testing costs constitute a significant part of the manufacturing cost.  This work was supported by the European Union in the context of the MORPHEUS project Num. 027342. R. Woods et al. (Eds.): ARC 2008, LNCS 4943, pp. 209–220, 2008. c  Springer-Verlag Berlin Heidelberg 2008