124 Original scientific paper  MIDEM Society Journal of Microelectronics, Electronic Components and Materials Vol. 43, No. 2(2013), 124 – 130 Simulation of semiconductor bulk trap influence on the electrical characteristics of the n-channel power VDMOS transistor Sanja Aleksić, Biljana Pešić and Dragan Pantić Department of Microelectronics, Faculty of Electronic Engineering, University of Niš, Niš, Serbia, Abstract: In this paper the impact of traps generated in semiconductor bulk due to High Electric Field Stress (HEFS) or irradiation of n-channel power VDMOSFET are presented. The influence of semiconductor bulk traps is expected, due to the fact that the current mainly flows vertically through the n-epitaxial layer and n+ substrate to drain contact. For the reverse engineering of the process flow and the simulation of electrical characteristics of power VDMOS transistor, Technology Computer-Aided Design (TCAD) software package tools from Silvaco are used. Taking the advantage of simulation, the influences of donor (DT) and acceptor (AT) traps generated in the semiconductor bulk on the electrical characteristics are separately analysed and discussed. Key words: TCAD, power VDMOSFET, donor and acceptor bulk traps Simulacija vpliva pasti v substratu n kanalnega močnostnega VDMOS tranzistorja na njegove električne lastnosti Povzetek: V članku so predstavljeni vplivi pasti v substratu n kanalnega močnostnega VDMOS tranzistorja zaradi sevanja ali vpliva visokega električnega polja (HEFS). Vpliv pasti se pričakuje zaradi vertikalnega toka preko epitaksijske plasti n in n+ substrata v kontakt. Za analizo električnih lastnosti tranzistorja je bila uporabljena TCAD programska oprema proizvajalca Silvaco. Simulacije omogočajo, da je vpliv akceptorskih in donorskih plasti obravnavan ločeno. Ključne besede: TCAD, močnostni VDMOSFET, donorske in akceptorske pasti v substratu * Corresponding Author’s e-mail: sanja.aleksic@elfak.ni.ac.rs 1 Introduction The advanced generation of power VDMOS transistors are designed for a wide range of switching and am- plifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. These components are widely used in various applications. Considering the facts that the design of highly reliable, high-speed and low power integrated circuits (IC) is the critical task in this procedure, it is very important to know how the power VDMOS transistor acts when it is exposed to various stresses, such as high electrical field stress or irradiation. In this cases the defects in the form of traps (which can be neutral or charged), are generated in ox- ide and semiconductor bulk, as well as at the Si/SiO 2 interface. They significantly influence on the electrical characteristics of semiconductor devices. The traps, generated at the Si/SiO 2 interface and in the gate ox- ide, have the dominant influence on the electrical char- acteristics of MOS transistors [1-7], while in the power VDMOS transistor the influence of generated traps in semiconductor bulk must be taken into account due to the fact that the current mainly flows vertically through the n-epitaxial layer and n + -substrate to drain contact. Further reducing in VDMOS transistor size continu- ally complicates the device physics and makes device modeling more sophisticated [8-10]. Because of that, complete fabrication process flow and device electri- cal characteristics simulation programs, as well as the