458 Applied Surface Science 38 (1989) 458-466 North-Holland, Amsterdam SELF-ALIGNED CoSi 2 AND TiW(N) LOCAL INTERCONNECT tIN A SUBIVJffCRON CMOS PROCESS R.D..I. VERHAAR, A.A. BOS, .LM.F.G. VAN LAAR.HOVEN, H. KRAAI.I and R.A.M. WOLTERS Pl~ilips Research Laboratories, 5600 JA Eindhoven, The Netherlands Received :20 March 1989; accepted for publication 31 March 1989 The integration aspects of a self-aligned CoSt2 and TiW(N) local interconnect technology in a submicron CMOS process are described. The effect of substrate type and dope on the final sheet resistance of CoSt2 has been investigated. A small influence of the dope concentration has been observed on the formation of CoSt, however no significant effect is measured on the sheet re~,;istapee of the finally formed CoSt2. The Co-St reaction has been found to be very sensitive to the St-Co interface condition. A sacrificial oxidation has proven to be a suitable method to ensure a proper reaction. An electrical testing method is presented, which has shown to be a very sensitive method to detect overgrowth (bridging) in the salicide process. Voltage contrast SEM analysis showed to be suitable to locate overgrowth. The use of the CoSt2 salicide process did not provoke any serious degradation of transistor performance or gate oxide integrity. The results are comparable with those of TiSi2. TiW(N) is reported to be a good material for local intercodnect in combination with CoSt2. The integration aspects of the TiW(N) local interconnect technology are discussed. The etching process of TiW(N) appears to be the most critical step. 1. Intr~ucfion Self-aligned silicidation technologies, to reduce the poly-Si line resistance, the contact resistance, and the sheet resistanc~ of the diffusion regions, are receiving increasing attention. TiSi 2 is by far the most widely accepted material for this technology [1]. However, the interest for CoSi 2 has increased rapidly over the last few years due to its potential advantages over TiSi 2 [2]. In order to obtain small full CMOS 6 transistor SRAM cells, a low ohmic local interconnect is desirable since it can be used to extend source/drain areas and it provides the possibility for buried contacts [3]. Due to the superior plasma etch resistance of CoSt 2 the number of materials which can be used to realise local interconnect is larger. TiW(N) is reported to be a suitable material for this technology [4]. The implementation of self-aligned CoSt 2 and TiW(N) local interconnect in an advanced submicron CMOS process is described in this paper. 0169-4332/89/$03.50 © Elsevier Science Publishers B.V. (North-Holland Physics Publishing Division)