CMOS single-ended-to-differential low-noise amplifier Toma ´ s Carrasco Carrillo à , Jose ´ Gabriel Macias-Montero, Aitor Osorio Martı ´, Javier Sieiro Co ´ rdoba, Jose ´ Marı ´a Lopez-Villegas Department of Electronics, University of Barcelona, C/Martı ´i Franque´s 1, 08028 Barcelona, Spain article info Keywords: CMOS Low-noise amplifier (LNA) Low-power–low-voltage Noise optimization RF AmI IEEE 802.15.4 abstract In this work, a low-power single-ended-to-differential low-noise amplifier (LNA) is reported. The circuit has been designed and optimized to be included in an IEEE 802.15.4 standard receiver. In order to minimize power consumption, active loads and currents mirrors have been replaced by optimized inductors and transformers. Moreover, an exhaustive study of the mixed-mode parameters has been carried out, enabling the definition of single-ended figures of merits in terms of mixed-mode S-parameters. The LNA has been implemented using a 0.35 mm RFCMOS technology. Performances are a noise figure of 4.3 dB, a power gain of 21 dB, and a phase balance of 180711 . Regarding non-linear behaviour, the obtained 1 dB-compression point obtained is 9.5 dB m while intermodulation intercept point is 3 dB m, dissipating 6 mA from 1.5 V supply voltage. & 2008 Elsevier B.V. All rights reserved. 1. Introduction Low-noise amplifiers (LNA) are one of the key components in receivers because it tends to dominate the sensitivity and noise figure (NF) of the whole system [1]. This sensitivity is directly related to both active and passive devices available in a given technology. Thus the chosen technology will have a high impact on the final specs that could be achievable. However, the specifications of the communication standard and product cost as well as small size, level of integration, power consumption are additional constraints that will complicate the technology selec- tion process. Actually, in high performance applications, LNA noise figures below 2 dB have been demonstrated [2–4] using integrated technologies such as SiGe, GaAs or improved CMOS (microma- chining, SOI, etc.). Nonetheless there are applications where the system specifi- cations are relaxed, e.g. in wireless sensor networks, enabling the use of conventional CMOS processes. The LNA proposed in this work is a part of the RF front-end receiver of a reduced functional device (RFD) intended to work in compliance with the IEEE 802.15.4 low-frequency band (European 868–868.6MHz) [5]. The key characteristic of the standard is its protocol simplicity and flexibility providing a reliable data transfer in a short-range operation (typically within a range of 10m). A summary of the most important specifications of the standard is shown in Table 1 . Due to the final application, i.e. a wireless sensor network, the RFD units must be tiny, consume a small amount of power, and have a very low final cost. Taking into account such constraints, RFCMOS 0.35 mm is a good technology option for the implementa- tion of a complete transceiver of the RFD unit. Once the framework, has been established, the designer must face three challenges. First, the choice of communication system architecture will have a strong influence on the possible circuit topologies of the LNA for achieving the specifications of the standard. Second, the designer should identify and apply the best design methodologies and strategies for archiving a low-voltage low-power (LVLP) circuit. And third, once the technology has been fixed, the LNA performance depends strongly on the quality of the passives components; therefore, the designer has to be able to evaluate their behaviour using full-wave electromagnetic simulators. In this work, the selected transceiver architecture uses one single-ended antenna for both transmission and reception paths that are split using an external switch, as shown in Fig. 1 . To minimize the effects of the common-mode noise, e.g. digital switching noise, the received signal must be processed differen- tially. Therefore, this assumption points out the need of a single- ended-to-differential LNA design. Commonly, out of chip passive BalUn has been used to convert single-ended signals to differ- ential signals. Unfortunately, it introduces losses increasing the system noise figure. To avoid these mentioned drawbacks, an active topology is preferred in this work. Moreover, to compensate the dynamic range of the complete system without increasing the total power consumption, a fully differential variable gain amplifier has been connected to LNA output. With this selected architecture, the system specifications are translated into the LNA block as a maximum NF of 7 dB, a minimum gain of 18 dB, and an input intercept point to the third harmonic (IIP3) of 10 dB m. ARTICLE IN PRESS Contents lists available at ScienceDirect journal homepage: www.elsevier.com/locate/vlsi INTEGRATION, the VLSI journal 0167-9260/$ - see front matter & 2008 Elsevier B.V. All rights reserved. doi:10.1016/j.vlsi.2008.11.003 à Corresponding author. Tel.: +34 93 40 39158; fax: +34 9340 33333. E-mail address: tcarrasco@el.ub.es (T.C. Carrillo). INTEGRATION, the VLSI journal 42 (2009) 304–311