Accurate modeling of the influence of back gate bias and interface roughness on the threshold voltage of nanoscale DG MOSFETs Abhijit Biswas ⇑ , Swagata Bhattacherjee Institute of Radio Physics and Electronics, University of Calcutta, 92 Acharya Prafulla Chandra Road, Kolkata 700 009, India article info Article history: Received 29 August 2011 Received in revised form 19 July 2012 Accepted 8 September 2012 Available online 11 October 2012 abstract An accurate 2-D analytical model regarding the influence of back gate bias V bg on the threshold voltage of double gate (DG) MOSFETs for a wide range of geometric dimensions and gate materials is presented. The threshold voltage V t and its variation have been determined with different geometric dimensions taking into account several effects such as quantum mechanical effects and the surface roughness effect for var- ious back gate bias conditions. Our theoretical calculations rely on the solution of 2-D Poisson’s equation while numerical simulation results are obtained from the numerical device simulator ATLAS. The shift in V t due to quantum effects and the surface roughness-induced effect has been calculated by employing the accurate value of ground state energy computed using variational approach for a finite rectangular quan- tum well as exists in a real DG MOS structure. Our investigations show that V t increases with increasing negative V bg and exhibits significant enhancement due to quantum effects and the surface roughness effect particularly for channel thickness below 5 nm. The margin of accuracy has been verified by com- paring our analytical and simulation results with reported simulation and experimental data for various devices. Ó 2012 Elsevier Ltd. All rights reserved. 1. Introduction The double-gate MOSFET has attracted considerable attention for ultimate CMOS scaling due to its better control on short chan- nel effects (SCEs), its ideal subthreshold slope of 60 mV/dec and its ability to get scaled down to a very short channel length [1–4]. The threshold voltage V t is an important electrical parameter related to the performance of the MOS device. For instance, a lower V t causes gate overdrive to increase while enhancing the leakage current exponentially [5]. V t depends not only on the process flow em- ployed during fabrication, material parameters, and geometrical dimensions of the device but also on the back gate bias voltage of the device; hence a specific value of the threshold voltage may be achieved by controlling the bias even without altering process parameters. Material parameters refer to channel doping concen- tration, dielectric constant, band gap, etc. whereas geometrical dimensions include channel length, oxide thickness and channel thickness. Most importantly, as the device dimensions shrink in the nanometer regime quantum-mechanical effects and the effect owing to surface roughness become significant in determining the accurate value of V t [6–9]. Usually ion implantation, complex doping profiles in the chan- nel and gate work function are exploited to adjust V t for MOS de- vices [10–12]. Considering the dependency of V t on various parameters at different levels, the employment of bias voltage to the back gate is likely to be the most dexterous technique to mod- ify the value of V t even after the device has been fabricated. The dependence of threshold voltage for DG MOSFETs with different geometrical dimensions and channel doping concentrations has al- ready been reported in the literature [13–15]. There have been extensive studies concerning the effects of bias voltage on the per- formance and on the key design parameters such as the threshold voltage, on-current, and off-current, of bulk MOSFETs [16–18]. The effect of body bias on different electrical parameters of MOS de- vices with different gate architectures was investigated experi- mentally as well as numerically using device simulation program [19]. Other studies involved measurements of the electrical param- eters such as the threshold voltage, on-current, off-current of bulk MOSFETs for a range of substrate bias voltages [16]. Additionally, there were also reports [17] regarding the influence of substrate bias on the breakdown progression in ultra-thin oxide pMOSFETs. On the front related to analog and RF applications, there were some notable studies on the body bias effect for partially depleted silicon on insulator (PDSOI) devices [18]. The influence of quantum- mechanical effects in shifting the threshold voltage of extremely scaled MOSFETs has been published by several research groups [20–22]. Recently, experimental findings of Uchida et al. [23] iden- tified that the surface roughness caused an enhanced shift of the threshold voltage particularly for ultra-thin body (UTB) SOI MOS- FETs. The modification of the threshold voltage V t due to quan- tum-mechanical effects and the effect of surface roughness has 0026-2714/$ - see front matter Ó 2012 Elsevier Ltd. All rights reserved. http://dx.doi.org/10.1016/j.microrel.2012.09.005 ⇑ Corresponding author. Tel.: +91 332350 9115; fax: +91 332350 5828. E-mail address: abiswas5@rediffmail.com (A. Biswas). Microelectronics Reliability 53 (2013) 363–370 Contents lists available at SciVerse ScienceDirect Microelectronics Reliability journal homepage: www.elsevier.com/locate/microrel