Characterization and performance comparison of the power DIMOS structure fabricated with a reduced thermal budget in 4H and 6H-SiC Vickram R. Vathulya*, Marvin H. White Lehigh University, Sherman Fairchild Center, Bethlehem, PA, 18015, USA Received 21 February 1999; received in revised form 4 July 1999; accepted 31 July 1999 Abstract In this work, a reduced thermal budget processing scheme using aluminum as the p-well dopant is investigated for the fabrication of the power DIMOS (Double Implanted MOSFET) in 4H and 6H-SiC in an eort to improve the on-state conduction. The on-state conduction in 4H-SiC devices is limited severely by low values of carrier mobility at the surface as compared with 6H-SiC. Surface mobilities extracted on lateral MOSFETs indicate the mobility values in 6H-SiC (40 cm 2 /Vs) are signi®cantly higher than in 4H-SiC (5 cm 2 /Vs). Therefore, even when step- bunching is avoided through the use of a reduced thermal budget, the intrinsic surface disorder in 4H-SiC is higher than in 6H-SiC and leads to degraded conduction at the surface. Moreover, mobility on accumulated surfaces is higher than on inverted surfaces in both polytypes. The relative insensitivity of surface mobility to gate bias and temperature changes does not conform to existing models for surface mobility necessitating the development of new models to explain carrier transport at implanted SiC surfaces. The present study suggests that unless the surface morphology of 4H-SiC is improved, the advantage of a higher vertical bulk mobility in 4H cannot be exploited and 6H will remain as the polytype of choice for the power DIMOS fabrication in SiC. # 2000 Elsevier Science Ltd. All rights reserved. 1. Introduction SiC has been a subject of intensive research for power device fabrication due to its wide bandgap, high breakdown ®eld strength and large thermal conduc- tivity. In particular, the 4H-SiC polytype has been intensively pursued by various groups for the fabrica- tion of vertical power devices due to its higher bulk mobility (10) in the vertical direction as compared to the other commercially available 6H-SiC polytype. However, since the o-axis angle (88) for epilayer growth on 4H-SiC substrates is higher than in 6H-SiC (3.58), step-bunching (due to the high temperature acti- vation anneal required for the boron doped p-well) is expected to be a more severe problem in MOS based power devices in 4H-SiC than in 6H-SiC. In order to evaluate the polytype suitability for the vertical power MOSFET (which has both bulk and surface conduction) fabrication in SiC, the relative impact of the above two eects on the electrical per- formance of the devices needs to be investigated. We report for the ®rst time on a comparison of the electri- cal performance of inversion mode Double Implanted Solid-State Electronics 44 (2000) 309±315 0038-1101/00/$ - see front matter # 2000 Elsevier Science Ltd. All rights reserved. PII: S0038-1101(99)00237-3 * Corresponding author. Tel.: +1-610-758-4518; fax: +1- 610-758-6705. E-mail address: viv2@lehigh.edu (V.R. Vathulya).