A Fast Design Space Exploration for VLIW Architectures Reza Yazdani, Hamed Sheidaeian, and Mostafa E. Salehi School of Electrical and Computer Engineering, University of Tehran, Tehran 14395-515, Iran {Yazdani67, sheidaeian , mersali}@ut.ac.ir Abstract— Design space exploration is referred to a search on possible architecture configurations of a system, to find the feasible and optimum solution for the desired application based on the defined objectives. The objective could be optimization of performance, power or area of the system. There are various numbers of algorithmic approaches for exploration. This paper presents a novel method for design space exploration on VLIW processors. Our proposed approach is mainly based on space pruning methodology using binary search tree. This method will be experimented on a specific VLIW embedded system. The focus of the exploration is on optimizing performance or area of the base architecture through finding the optimum number of resources and cache sizes. Experimental results proves that our algorithm gets to the optimum solution comparing with the solution resulted by exhaustive approach, and also outperforms this approach through a logarithmic order against a polynomial one. Keywords: Design Space Exploration (DSE), VLIW architecture, Binary Search Pruning I. INTRODUCTION There are large numbers of possibilities for mapping various architectural components to the hardware resources. Finding all of these possibilities manually is difficult and so time-consuming. Design choices create a large space of possible design solutions called design space. Design Space Exploration (DSE) searches through the design space to find feasible and optimal solutions. DSE methodology has some inputs (an application and a fixed hardware platform) and an optimization function based on intended objectives (such as performance and/or area) which finally yields the optimum configuration. A straightforward approach in DSE is the exhaustive search of all points in the space. The main challenges of this method are complication of various conflicting requirements and dealing with an exponential number of design alternatives. The solutions are DSE automation and improving exploration time by pruning the design space. Some algorithmic approaches of DSE are simple and non-scalable brute force, but there are also complex mechanisms mimicking optimization methods such as genetic evolution. All of these approaches share a common set of capabilities [1]:  Design Space Generation: The ability to view, represent and encode the complete set of potential and feasible design architectures made up of different combinations of platform components.  Model Refinement: The ability to generate an executable model of the application executing on a given platform architecture.  Assessment: The ability to assess a set of parameters for the application executing on the given architecture.  Selection: The ability to test the fitness of a pool of design points, and to eventually prune the design space from a large pool to a smaller, Pareto-optimal set. Three major areas of interest in a DSE subsystem are Design Space Representation, Metrics and Exploration Algorithms. Most of the research efforts on design space exploration for system level design automation have been oriented towards the exploration strategy [2, 3, 4, 5 and 6]. The algorithms implementing explicit strategies allow easier evaluation and comparisons among different complex exploration techniques like linear programming, traditional multi-objective optimization, hierarchical decomposition of the design space and heuristic strategies. Current state-of-the- art in system-level DSE often deploys population-based Monte Carlo optimization algorithms like hill climbing, simulated annealing, artificial neural network, colony optimization and genetic-fuzzy algorithms. By adjusting the parameters, or by modifying the algorithm to include domain-specific knowledge, these algorithms can be customized for different DSE problems. In this paper we will propose a novel heuristic method for design space exploration on VLIW processors. The main strategy of our heuristic DSE approach is based on binary search pruning. Our proposed schema is designed for VEX VLIW processor and the focus of the exploration is mostly on cluster resources (ALU, Multiply, and Issue Width) and cache sizes (instruction and data caches). This schema can also be used for other embedded systems with various numbers of resources. The rest of this paper is organized as follows: Section 2 presents preliminary discussions about DSE engines, DSE frameworks and related work on VLIW design space exploration. Section 3 introduces VEX architectures and their features. Section 4 illustrates our proposed DSE methodology. Section 5 evaluates the algorithms through experimental results. This section compares the iteration number of our method with exhaustive exploration. Besides that, we compare performance-optimum and area-optimum results of the proposed algorithms to that of exhaustive method. Section 6 presents the conclusion of paper and our promotion. II. RELATED WORK There are numerous of DSE engines using different algorithms, for example in [7] System Co-Designer uses genetic algorithms for intelligent random explorations; DESERT [8] relies on an ordered binary decision diagrams based on symbolic search; Sesame [9] has support for an exhaustive simulation-based DSE as well as heuristic explorations using genetic algorithms or other DSE methods; and some other engines are based on artificial neural network schemas and local regression modeling [10, 11]. As the complexity of the systems increases, manual exploration of the design space becomes intractable and automated approaches to DSE become imperative. Different search techniques named solvers are invented to automate the 978-1-4799-4409-5/14/$31.00 ©2014 IEEE The 22nd Iranian Conference on Electrical Engineering (ICEE 2014), May 20-22, 2014, Shahid Beheshti University 856