Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories Rajeshwar S. Sable 1 , Ravindra P. Saraf 2 , Rubin A. Parekhji 3 and Arun N. Chandorkar 4 1 Tejas Networks Pvt. Ltd. , Bangalore, India. Email: rajeshwar@india.tejasnetworks.com 2 Intel Technology India Pvt. Ltd., Bangalore, India. Email: ravindra.p.saraf@intel.com 3 Texas Instruments (India) Pvt. Ltd., Bangalore, India. Email: parekhji@ti.com 4 Indian Institute of Technology, Mumbai, India. Email: anc@ee.iitb.ac.in Abstract Traditional tests for memories are based on conventional fault models, involving the address decoder, individual memory cells and a limited coupling between them. The algorithms used in these tests have been successively augmented to consider stronger coupling conditions. Built-in self-test (BIST) solutions for testing memories today incorporate hardware for test pattern generation and application for a variety of these algorithms. This paper presents a BIST implementation for detection of neighbourhood pattern sensitive faults (NPSFs) in random access memories (RAMs). These faults are of different classes and types. More specifically, active, passive and static faults for distance 1 and 2 neighbourhoods, of types 1 and 2, are considered. It is shown how the proposed address generation and test pattern generation schemes can be made scaleable for the given fault type under consideration. Keywords: Built-in self-test for memories, neighbourhood pattern sensitive faults, programmable BIST. 1. Introduction Shrinking feature sizes and increase in the levels of integration have significantly impacted the design and test of random access memories (RAMs). While memory cells and architectures have become increasingly compact, they are now also susceptible to increasingly diverse failure mechanisms. This has rendered the traditional memory test methods inadequate, either in terms of their defect coverage or in terms of the test application time. Built-in self-test (BIST) methods for testing RAMs, based on conventional March tests and their extensions, are becoming popular. These tests are easy to implement, have a cycle count complexity which is linear to the number of bits or words addressed, and provide good fault coverage for functional faults and some structural faults, covering the address decoder, individual memory cells and a limited coupling between them [1]. BIST also offers other well-known advantages, which will not be repeated here [2,3]). Existing BIST implementations for memories are, however, inadequate for some other fault models like stronger and widespread coupling faults. Hence, to ensure the desired defect coverage in a memory core, it is necessary to consider these newer fault models and provide a matching BIST implementation for effective test generation. It is also important to make this implementation programmable for the desired combination of fault coverage and test time so that BIST can be efficiently used. This paper describes a BIST technique for the detection of neighbourhood pattern sensitive faults (NPSFs) in random access memories. Although the NPSF model is not new, it is now becoming important in deep-submicron processes, especially for DRAMs [4]. Also, the fault model scales with the neighbourhood size. Traditional March tests are not adequate for detection of such NPSFs [1,5]. Hence the proposed BIST mechanism for detecting NPSFs is designed to correspondingly match the faults being considered. The salient features of this BIST implementation are: (a) It uses the well-known tiling method and employs a parallel access mechanism to memories to reduce the cycle count. (b) It employs a bit-slice architecture for the test pattern generator to generate a Eulerian sequence for covering the cells in the neighbourhood. (c) The BIST implementation, based on the proposed address and test pattern generation schemes, is scaleable for four different NPSF models, (based on distance 1 and 2, and types 1 and 2), for active, passive and static faults. This implementation covers stuck-at faults, transition faults, inversion coupling faults, idempotent coupling faults and static coupling faults, besides the NPSFs mentioned above. As complete rows of cells are accessed for read and write operations, this test is better suited for wider memories. (According to the authors, this is the first time that such a BIST implementation for NPSFs is being reported). This paper is organized into six sections. Section 2 provides an overview of NPSFs, their classes and types, and challenges in their detection. Section 3 describes the basic BIST technique for detection for one class of NPSFs, together with its implementation. This implementation is extended in Section 4 to include other types of NPSFs. The overall BIST operation is summarised in Section 5. Section 6 concludes the paper. 2. Overview of Neighbourhood Pattern Sensitive Faults A pattern sensitive fault is a conditional coupling fault in which the content of a memory cell or the ability to change its content is influenced by a certain bit pattern in other cells in the memory [1]. Here the data retention and transition of the victim cell are affected by a set of aggressor cells. A neighbourhood pattern sensitive fault (NPSF) is a special case of pattern sensitive faults, wherein the influencing (coupling) cells are in the neighbourhood of the influenced (coupled) cell. The coupled cell is called the base (or victim) cell and the coupling cells are called the deleted neighbourhood cells. (The neighbourhood includes all the cells in the deleted neighbourhood as well as the base cell). Refer to Figure 1. Here the cell V represents the base or victim cell, while the cells B, W and C represent the deleted neighbourhood. 2.1. Classification of NPSFs Different NPSFs can be grouped based on the nature of faults in the base cell and on the neighbourhood: Active NPSF: The base cell changes its content due to a change in the deleted neighbourhood pattern. To test these faults, the base cell should be read in state 0 and state 1 for all possible transitions in the deleted neighbourhood. Passive NPSF: The content of the base cell cannot be changed due to a certain neighbourhood pattern. Every base cell has to be Proceedings of the 17th International Conference on VLSI Design (VLSID’04) 1063-9667/04 $ 20.00 © 2004 IEEE Authorized licensed use limited to: INDIAN INSTITUTE OF TECHNOLOGY BOMBAY. Downloaded on October 24, 2008 at 06:52 from IEEE Xplore. Restrictions apply.